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Octal LNA/VGA/AAF/12-Bit ADC and CW I/Q Demodulator AD9276
FEATURES
8 channels of LNA, VGA, AAF, ADC, and I/Q demodulator Low noise preamplifier (LNA) Input-referred noise: 0.75 nV/Hz typical at 5 MHz (gain = 21.3 dB) SPI-programmable gain: 15.6 dB/17.9 dB/21.3 dB Single-ended input: VIN maximum = 733 mV p-p/ 550 mV p-p/367 mV p-p Dual-mode active input impedance matching Bandwidth (BW) > 100 MHz Full-scale (FS) output: 4.4 V p-p differential Variable gain amplifier (VGA) Attenuator range: -42 dB to 0 dB Postamp gain: 21 dB/24 dB/27 dB/30 dB Linear-in-dB gain control Antialiasing filter (AAF) Programmable second-order LPF from 8 MHz to 18 MHz Programmable HPF Analog-to-digital converter (ADC) 12 bits at 10 MSPS to 80 MSPS SNR: 70 dB SFDR: 75 dB Serial LVDS (ANSI-644, IEEE 1596.3 reduced range link) Data and frame clock outputs CW mode I/Q demodulator Individual programmable phase rotation Output dynamic range per channel >160 dBFS/Hz Low power: 195 mW per channel at 12 bits/40 MSPS (TGC), 94 mW per channel for CW Doppler Flexible power-down modes Overload recovery in <10 ns Fast recovery from low power standby mode: <2 s 100-lead TQFP_EP
AVDD1 AVDD2 PDWN
APPLICATIONS
Medical imaging/ultrasound Automotive radar
PRODUCT HIGHLIGHTS
1. Small Footprint. Eight channels are contained in a small, space-saving package. Full TGC path, ADC, and I/Q demodulator contained within a 100-lead, 16 mm x 16 mm TQFP. Low Power. In TGC mode, low power of 195 mW per channel at 40 MSPS. In CW mode, ultralow power of 94 mW per channel. Integrated High Dynamic Range I/Q Demodulator with Phase Rotation. Ease of Use. A data clock output (DCO) operates up to 480 MHz and supports double data rate (DDR) operation. User Flexibility. Serial port interface (SPI) control offers a wide range of flexible features to meet specific system requirements. Integrated Second-Order Antialiasing Filter. This filter is placed before the ADC and is programmable from 8 MHz to 18 MHz.
2.
3. 4.
5.
6.
FUNCTIONAL BLOCK DIAGRAM
STBY DRVDD
LO-A TO LO-H LOSW-A TO LOSW-H LI-A TO LI-H LG-A TO LG-H LNA VGA
I/Q DEMODULATOR
8 CHANNELS
AAF
12-BIT ADC
SERIAL LVDS
DOUTA+ TO DOUTH+ DOUTA- TO DOUTH-
LO GENERATION
REFERENCE
SERIAL PORT INTERFACE
DATA RATE MULTIPLIER
FCO+ FCO- DCO+ DCO-
GAIN+ GAIN-
CWI- CWI+ CWQ- CWQ+
4LO+
4LO-
GPO[0:3]
SCLK
RESET
VREF
SDIO
CSB
RBIAS
CLK+
CLK-
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved.
08180-001
AD9276 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Product Highlights ........................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications..................................................................................... 4 AC Specifications.......................................................................... 4 Digital Specifications ................................................................... 7 Switching Specifications .............................................................. 8 ADC Timing Diagrams ............................................................... 9 Absolute Maximum Ratings.......................................................... 10 Thermal Impedance ................................................................... 10 ESD Caution ................................................................................ 10 Pin Configuration and Function Descriptions ........................... 11 Typical Performance Characteristics ........................................... 14 TGC Mode ................................................................................... 14 CW Doppler Mode ..................................................................... 17 Equivalent Circuits ......................................................................... 19 Theory of Operation ...................................................................... 21 Ultrasound .................................................................................. 21 Channel Overview ..................................................................... 22 Input Overdrive .......................................................................... 25 CW Doppler Operation............................................................. 25 TGC Operation ........................................................................... 29 ADC ............................................................................................. 33 Clock Input Considerations ...................................................... 33 Digital Outputs and Timing ..................................................... 35 Serial Port Interface (SPI) .............................................................. 39 Hardware Interface..................................................................... 40 Memory Map .................................................................................. 41 Reading the Memory Map Table .............................................. 41 Reserved Locations .................................................................... 41 Default Values ............................................................................. 41 Logic Levels ................................................................................. 41 Applications Information .............................................................. 45 Power and Ground Recommendations ................................... 45 Exposed Paddle Thermal Heat Slug Recommendations ...... 45 Outline Dimensions ....................................................................... 46 Ordering Guide .......................................................................... 46
REVISION HISTORY
7/09--Revision 0: Initial Version
Rev. 0 | Page 2 of 48
AD9276 GENERAL DESCRIPTION
The AD9276 is designed for low cost, low power, small size, and ease of use. It contains eight channels of a variable gain amplifier (VGA) with a low noise preamplifier (LNA); an antialiasing filter (AAF); a 12-bit, 10 MSPS to 80 MSPS analog-todigital converter (ADC); and an I/Q demodulator with programmable phase rotation. Each channel features a variable gain range of 42 dB, a fully differential signal path, an active input preamplifier termination, a maximum gain of up to 52 dB, and an ADC with a conversion rate of up to 80 MSPS. The channel is optimized for dynamic performance and low power in applications where a small package size is critical. The LNA has a single-ended-to-differential gain that is selectable through the SPI. The LNA input noise is typically 0.75 nV/Hz at a gain of 21.3 dB, and the combined input-referred noise of the entire channel is 0.85 nV/Hz at maximum gain. Assuming a 15 MHz noise bandwidth (NBW) and a 21.3 dB LNA gain, the input SNR is roughly 92 dB. In CW Doppler mode, each LNA output drives an I/Q demodulator. Each demodulator has independently programmable phase rotation through the SPI with 16 phase settings. The AD9276 requires a LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO) for capturing data on the output and a frame clock (FCO) trigger for signaling a new output byte are provided. Powering down individual channels is supported to increase battery life for portable applications. A standby mode option allows quick power-up for power cycling. In CW Doppler operation, the VGA, AAF, and ADC are powered down. The power of the TGC path scales with selectable ADC speed power modes. The ADC contains several features designed to maximize flexibility and minimize system cost, such as a programmable clock, data alignment, and programmable digital test pattern generation. The digital test patterns include built-in fixed patterns, built-in pseudorandom patterns, and custom user-defined test patterns entered via the serial port interface. Fabricated in an advanced CMOS process, the AD9276 is available in a 16 mm x 16 mm, RoHS compliant, 100-lead TQFP. It is specified over the industrial temperature range of -40C to +85C.
Rev. 0 | Page 3 of 48
AD9276 SPECIFICATIONS
AC SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, fIN = 5 MHz, RS = 50 , LNA gain = 21.3 dB, LNA bias = high, PGA gain = 27 dB, GAIN- = 0.8 V, AAF LPF cutoff = fSAMPLE/3 (Mode I/Mode II), fSAMPLE/4.5 (Mode III), HPF cutoff = LPF cutoff/20.7 (default), Mode I = fSAMPLE = 40 MSPS, Mode II = fSAMPLE = 65 MSPS, Mode III = fSAMPLE = 80 MSPS, full temperature, ANSI-644 LVDS mode, unless otherwise noted. Table 1.
Parameter 1 LNA CHARACTERISTICS Gain Input Voltage Range (Single-Ended) Test Conditions/Comments Single-ended input to differential output Single-ended input to single-ended output LNA output limited to 4.4 V p-p differential output LNA gain = 15.6 dB LNA gain = 17.9 dB LNA gain = 21.3 dB Min Typ 15.6/17.9/21.3 9.6/11.9/15.3 Max Unit dB dB
Input Common Mode (LI-x, LG-x) Output Common Mode (LO-x) Output Common Mode (LOSW-x) Input Resistance (LI-x)
Switch off Switch on RFB = 250 RFB = 500 RFB =
Input Capacitance (LI-x) -3 dB Bandwidth Input Noise Voltage
733 550 367 1.0 1.5 High-Z 1.5 50 100 15 22 100 0.98 0.86 0.75 1 1.0 0.8 0.5 4.8 4.1 3.2 3.4 2.8 2.3
mV p-p mV p-p mV p-p V V V k pF MHz nV/Hz nV/Hz nV/Hz pA/Hz V p-p V p-p V p-p dB dB dB dB dB dB
Input Noise Current 1 dB Input Compression Point
Noise Figure Active Termination Matched
Unterminated
RS = 0 , RFB = LNA gain = 15.6 dB LNA gain = 17.9 dB LNA gain = 21.3 dB RFB = GAIN+ = 0 V LNA gain = 15.6 dB LNA gain = 17.9 dB LNA gain = 21.3 dB RS = 50 LNA gain = 15.6 dB, RFB = 200 LNA gain = 17.9 dB, RFB = 250 LNA gain = 21.3 dB, RFB = 350 LNA gain = 15.6 dB, RFB = LNA gain = 17.9 dB, RFB = LNA gain = 21.3 dB, RFB =
FULL-CHANNEL (TGC) CHARACTERISTICS AAF Low-Pass Cutoff In Range In Range AAF Bandwidth Tolerance Group Delay Variation Input-Referred Noise Voltage
-3 dB, programmable
8 10
18
MHz % ns nV/Hz nV/Hz nV/Hz
f = 1 MHz to 18 MHz, GAIN+ = 0 V to 1.6 V GAIN+ = 1.6 V, RFB = LNA gain = 15.6 dB LNA gain = 17.9 dB LNA gain = 21.3 dB
Rev. 0 | Page 4 of 48
0.5 1.26 1.04 0.85
AD9276
Parameter 1 Noise Figure Active Termination Matched Mode I/Mode II/Mode III Test Conditions/Comments GAIN+ = 1.6 V, RS = 50 LNA gain = 15.6 dB, RFB = 200 LNA gain = 17.9 dB, RFB = 250 LNA gain = 21.3 dB, RFB = 350 LNA gain = 15.6 dB, RFB = LNA gain = 17.9 dB, RFB = LNA gain = 21.3 dB, RFB = No signal, correlated/uncorrelated -35 fIN = 5 MHz at -10 dBFS, GAIN+ = 0 V fIN = 5 MHz at -1 dBFS, GAIN+ = 1.6 V Harmonic Distortion Mode I/Mode II/Mode III Second Harmonic Third Harmonic Two-Tone Intermodulation (IMD3) 65/64/63 57/56/54.5 Min Typ 8.0/7.7/7.6 6.6/6.2/6.1 4.7/4.5/4.4 4.7 3.7 2.8 -30 +35 Max Unit dB dB dB dB dB dB dB LSB dBFS dBFS
Unterminated
Correlated Noise Ratio Output Offset Signal-to-Noise Ratio (SNR) Mode I/Mode II/Mode III
Channel-to-Channel Crosstalk Channel-to-Channel Delay Variation PGA Gain GAIN ACCURACY Gain Law Conformance Error Mode I/Mode II/Mode III
fIN = 5 MHz at -10 dBFS, GAIN+ = 0 V fIN = 5 MHz at -1 dBFS, GAIN+ = 1.6 V fIN = 5 MHz at -10 dBFS, GAIN+ = 0 V fIN = 5 MHz at -1 dBFS, GAIN+ = 1.6 V fRF1 = 5.015 MHz, fRF2 = 5.020 MHz, ARF1 = 0 dB, ARF2 = -20 dB, GAIN+ = 1.6 V, IMD3 relative to ARF2 fIN = 5 MHz at -1 dBFS Overrange condition 2 Full TGC path, fIN = 5 MHz, GAIN+ = 0 V to 1.6 V Differential input to differential output 25C 0 < GAIN+ < 0.16 V 0.16 V < GAIN+ < 1.44 V 1.44 V < GAIN+ < 1.6 V -1.5/-1.5/ -1.6 -1.5/-1.5/ -1.6 -1.5
-62/-58/-55 -60/-61/-58 -71/-60/-60 -57/-55/-56 -55
dBc dBc dBc dBc dBc
-70 -65 0.3 21/24/27/30 1.5 +1.5/+1.5/ +1.6 +1.5/+1.5/ +1.6 +1.5
dB dB Degrees dB dB dB dB dB dB V dB dB/V ns M k MHz Degrees V mA
-2.5
Linear Gain Error Channel-to-Channel Matching GAIN CONTROL INTERFACE Normal Operating Range Gain Range Scale Factor Response Time GAIN+ Impedance GAIN- Impedance CW DOPPLER MODE LO Frequency Phase Increment Output DC Bias (Single-Ended) Maximum Output Swing Transconductance (Differential)
GAIN+ = 0.8 V, normalized for ideal AAF loss 0.16 V < GAIN+ < 1.44 V
0.1 0 -42 28.5 750 10 70 1 22.5 1.5 1.25 10 1.6 0
GAIN+ = 0 V to 1.6 V 42 dB change Single-ended Single-ended fLO = f4LO/4 Per channel CWI+, CWI-, CWQ+, CWQ- Per CWI+, CWI-, CWQ+, CWQ-, per channel enabled Demodulated IOUT/VIN, each I or Q output LNA gain = 15.6 dB LNA gain = 17.9 dB LNA gain = 21.3 dB
1.8 2.4 3.5
mA/V mA/V mA/V
Rev. 0 | Page 5 of 48
AD9276
Parameter 1 Input-Referred Noise Voltage Test Conditions/Comments RS = 0 , RFB = LNA gain = 15.6 dB LNA gain = 17.9 dB LNA gain = 21.3 dB RS = 50 , RFB = LNA gain = 15.6 dB LNA gain = 17.9 dB LNA gain = 21.3 dB RS = 0 , RFB = LNA gain = 15.6 dB LNA gain = 17.9 dB LNA gain = 21.3 dB -3 dBFS input, fRF = 2.5 MHz, f4LO = 10 MHz, 1 kHz offset fRF1 = 5.015 MHz, fRF2 = 5.020 MHz, f4LO = 20 MHz, ARF1 = 0 dB, ARF2 = -20 dB, IMD3 relative to ARF2 I to Q, all phases, 1 I to Q, all phases, 1 Phase I to I, Q to Q, 1 Amplitude I to I, Q to Q, 1 Min Typ 1.5 1.4 1.3 5.7 5.3 4.8 164 162 160 155 -58 Max Unit nV/Hz nV/Hz nV/Hz dB dB dB dBFS/Hz dBFS/Hz dBFS/Hz dBc/Hz dB
Noise Figure
Input-Referred Dynamic Range
Output-Referred SNR Two-Tone Intermodulation (IMD3)
Quadrature Phase Error I/Q Amplitude Imbalance Channel-to-Channel Matching POWER SUPPLY Mode I/Mode II/Mode III AVDD1 AVDD2 DRVDD IAVDD1 IAVDD2
0.15 0.015 0.5 0.25
Degrees dB Degrees dB
1.7 2.7 1.7 TGC mode CW Doppler mode TGC mode, no signal CW Doppler mode per channel enabled, no signal TGC mode, no signal CW Doppler mode with eight channels enabled, no signal
1.8 3.0 1.8 190/263/317 15 365 30 49/51/52 1560/1690/ 1780 750
1.9 3.6 1.9
V V V mA mA mA mA mA mW mW
IDRVDD Total Power Dissipation (Including Output Drivers)
1800/1940/ 2050
Power-Down Dissipation Standby Power Dissipation Power Supply Rejection Ratio (PSRR) ADC RESOLUTION ADC REFERENCE Output Voltage Error Load Regulation at 1.0 mA Input Resistance
1
5 175/200/210 1.6 12 VREF = 1 V VREF = 1 V 20 2 6
mW mW mV/V Bits mV mV k
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed. 2 The overrange condition is specified as being 6 dB more than the full-scale input range.
Rev. 0 | Page 6 of 48
AD9276
DIGITAL SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, fIN = 5 MHz, full temperature, unless otherwise noted. Table 2.
Parameter 1 CLOCK INPUTS (CLK+, CLK-) Logic Compliance Differential Input Voltage 2 Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance CW 4LO INPUTS (4LO+, 4LO-) Logic Compliance Differential Input Voltage2 Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC INPUTS (PDWN, STBY, SCLK, RESET) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (CSB) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (SDIO) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC OUTPUT (SDIO) 3 Logic 1 Voltage (IOH = 800 A) Logic 0 Voltage (IOL = 50 A) DIGITAL OUTPUTS (DOUTx+, DOUTx-), (ANSI-644)1 Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) DIGITAL OUTPUTS (DOUTx+, DOUTx-), (LOW POWER, REDUCED SIGNAL OPTION)1 Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) LOGIC OUTPUTS (GPO0, GPO1, GPO2, GPO3) Logic 0 Voltage (IOL = 50 A)
1
Temperature
Min
Typ
Max
Unit
CMOS/LVDS/LVPECL Full Full 25C 25C 250 1.2 20 1.5 CMOS/LVDS/LVPECL Full Full 25C 25C Full Full 25C 25C Full Full 25C 25C Full Full 25C 25C Full Full 250 1.2 20 1.5 1.2 30 0.5 1.2 70 0.5 1.2 0 30 2 1.79 0.05 LVDS Full Full 247 1.125 Offset binary 454 1.375 mV V DRVDD + 0.3 0.3 3.6 0.3 3.6 0.3 mV p-p V k pF V V k pF V V k pF V V k pF V V mV p-p V k pF
LVDS Full Full 150 1.10 Offset binary Full 0.05 V 250 1.30 mV V
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed. 2 Specified for LVDS and LVPECL only. 3 Specified for 13 SDIO pins sharing the same connection.
Rev. 0 | Page 7 of 48
AD9276
SWITCHING SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, fIN = 5 MHz, full temperature, unless otherwise noted. Table 3.
Parameter 1 CLOCK 2 Clock Rate 40 MSPS (Mode I) 65 MSPS (Mode II) 80 MSPS (Mode III) Clock Pulse Width High (tEH) Clock Pulse Width Low (tEL) OUTPUT PARAMETERS2, 3 Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) FCO Propagation Delay (tFCO) DCO Propagation Delay (tCPD) 4 DCO to Data Delay (tDATA)4 DCO to FCO Delay (tFRAME)4 Data-to-Data Skew (tDATA-MAX - tDATA-MIN) Wake-Up Time (Standby), GAIN+ = 0.5 V Wake-Up Time (Power-Down) Pipeline Latency APERTURE Aperture Uncertainty (Jitter) LO GENERATION 4LO Frequency LO Divider RESET Setup Time 5 LO Divider RESET Hold Time5 LO Divider RESET High Pulse Width
1
Temperature
Min
Typ
Max
Unit
Full Full Full Full Full Full Full Full Full Full Full Full Full 25C 25C Full
10 10 10 6.25 6.25 (tSAMPLE/2) + 1.5 (tSAMPLE/2) + 2.3 300 300 (tSAMPLE/2) + 2.3 tFCO + (tSAMPLE/24) (tSAMPLE/24) (tSAMPLE/24) 100 2 1 8
40 65 80
MHz MHz MHz ns ns ns ps ps ns ns ps ps ps s ms Clock cycles ps rms
(tSAMPLE/2) + 3.1
(tSAMPLE/2) + 1.5 (tSAMPLE/24) - 300 (tSAMPLE/24) - 300
(tSAMPLE/2) + 3.1 (tSAMPLE/24) + 300 (tSAMPLE/24) + 300 350
25C Full Full Full Full 4 5 5 20
<1 40
MHz ns ns ns
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed. Can be adjusted via the SPI. 3 Measurements were made using a part soldered to FR-4 material. 4 tSAMPLE/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles. 5 RESET edge to rising 4LO edge.
2
Rev. 0 | Page 8 of 48
AD9276
ADC TIMING DIAGRAMS
N-1
AIN
N
CLK-
tEH
tEL
CLK+
tCPD
DCO-
DCO+
tFCO
FCO-
tFRAME
FCO+
tPD
DOUTx- MSB N-8 D10 N-8 D9 N-8 D8 N-8 D7 N-8
tDATA
D6 N-8 D5 N-8 D4 N-8 D3 N-8 D2 N-8 D1 N-8 D0 N-8 MSB N-7 D10 N-7
DOUTx+
Figure 2. 12-Bit Data Serial Stream (Default)
N-1
AIN
N
tEH
CLK-
tEL
CLK+
tCPD
DCO-
DCO+
tFCO
FCO-
tFRAME
FCO+
tPD
DOUTx- LSB N-8 DOUTx+ D0 N-8 D1 N-8 D2 N-8 D3 N-8
tDATA
D4 N-8 D5 N-8 D6 N-8 D7 N-8 D8 N-8 D9 N-8 D10 N-8 LSB N-7 D0 N-7
08180-003
Figure 3. 12-Bit Data Serial Stream, LSB First
Rev. 0 | Page 9 of 48
08180-002
AD9276 ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter AVDD1 to GND AVDD2 to GND DRVDD to GND GND to GND AVDD2 to AVDD1 AVDD1 to DRVDD AVDD2 to DRVDD Digital Outputs (DOUTx+, DOUTx-, DCO+, DCO-, FCO+, FCO-) to GND CLK+, CLK-, SDIO to GND LI-x, LO-x, LOSW-x to GND CWI-, CWI+, CWQ-, CWQ+ to GND PDWN, STBY, SCLK, CSB to GND GAIN+, GAIN-, RESET, 4LO+, 4LO-, GPO0, GPO1, GPO2, GPO3 to GND RBIAS, VREF to GND Operating Temperature Range (Ambient) Storage Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Rating -0.3 V to +2.0 V -0.3 V to +3.9 V -0.3 V to +2.0 V -0.3 V to +0.3 V -2.0 V to +3.9 V -2.0 V to +2.0 V -2.0 V to +3.9 V -0.3 V to +2.0 V -0.3 V to +2.0 V -0.3 V to +3.9 V -0.3 V to +3.9 V -0.3 V to +2.0 V -0.3 V to +3.9 V -0.3 V to +2.0 V -40C to +85C -65C to +150C 150C 300C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL IMPEDANCE
Table 5.
Airflow Velocity (m/s) 0.0 1.0 2.5
1
JA1 20.3 14.4 12.9
JB 7.6
JC 4.7
Unit C/W C/W C/W
JA for a 4-layer PCB with solid ground plane (simulated). Exposed pad soldered to PCB.
ESD CAUTION
Rev. 0 | Page 10 of 48
AD9276 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
100 LOSW-E 76 LOSW-D 85 AVDD2 91 AVDD2 86 AVDD2 82 RESET 89 RBIAS 88 GAIN+ 87 GAIN- 95 CWQ+ 94 CWQ- 81 GPO3 80 GPO2 79 GPO1 78 GPO0 90 VREF 93 CWI+ 84 4LO+ 92 CWI- 83 4LO- 77 LO-D 99 LO-E 98 GND 97 GND 96 GND
LI-E 1 LG-E 2 AVDD2 3 AVDD1 4 LO-F 5 LOSW-F 6 LI-F 7 LG-F 8 AVDD2 9 AVDD1 10 LO-G 11 LOSW-G 12 LI-G 13 LG-G 14 AVDD2 15 AVDD1 16 LO-H 17 LOSW-H 18 LI-H 19 LG-H 20 AVDD2 21 AVDD1 22 CLK- 23 CLK+ 24 AVDD1 25
DRVDD 26
PIN 1 INDICATOR
75 74 73 72
LI-D LG-D AVDD2 AVDD1 LO-C LOSW-C LI-C LG-C AVDD2 AVDD1 LO-B LOSW-B LI-B LG-B AVDD2 AVDD1 LO-A LOSW-A LI-A LG-A AVDD2 AVDD1 CSB SDIO SCLK
EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE)
71 70
AD9276
TOP VIEW (Not to Scale)
69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DOUTH- 27
DOUTH+ 28
DOUTG- 29
DOUTG+ 30
DOUTF- 31
DOUTF+ 32
DOUTE- 33
DOUTE+ 34
DCO- 35
DCO+ 36
FCO- 37
FCO+ 38
DOUTD- 39
DOUTD+ 40
DOUTC- 41
DOUTC+ 42
DOUTB- 43
DOUTB+ 44
DOUTA- 45
DOUTA+ 46
DRVDD 47
STBY 48
PDWN 49
AVDD1 50
NOTES 1. THE EXPOSED PAD SHOULD BE TIED TO A QUIET ANALOG GROUND.
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. 0, 96, 97, 98 1 2 3, 9, 15, 21, 55, 61, 67, 73, 85, 86, 91 4, 10, 16, 22, 25, 50, 54, 60, 66, 72 5 6 7 8 11 12 13 14 17 18 19 20 Name GND LI-E LG-E AVDD2 AVDD1 LO-F LOSW-F LI-F LG-F LO-G LOSW-G LI-G LG-G LO-H LOSW-H LI-H LG-H Description Ground. Exposed paddle should be tied to a quiet analog ground. LNA Analog Input for Channel E. LNA Ground for Channel E. 3.0 V Analog Supply. 1.8 V Analog Supply. LNA Analog Inverted Output for Channel F. LNA Analog Switched Output for Channel F. LNA Analog Input for Channel F. LNA Ground for Channel F. LNA Analog Inverted Output for Channel G. LNA Analog Switched Output for Channel G. LNA Analog Input for Channel G. LNA Ground for Channel G. LNA Analog Inverted Output for Channel H. LNA Analog Switched Output for Channel H. LNA Analog Input for Channel H. LNA Ground for Channel H.
Rev. 0 | Page 11 of 48
08180-004
AD9276
Pin No. 23 24 26, 47 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 48 49 51 52 53 56 57 58 59 62 63 64 65 68 69 70 71 74 75 76 77 78 79 80 81 82 83 84 87 88 Name CLK- CLK+ DRVDD DOUTH- DOUTH+ DOUTG- DOUTG+ DOUTF- DOUTF+ DOUTE- DOUTE+ DCO- DCO+ FCO- FCO+ DOUTD- DOUTD+ DOUTC- DOUTC+ DOUTB- DOUTB+ DOUTA- DOUTA+ STBY PDWN SCLK SDIO CSB LG-A LI-A LOSW-A LO-A LG-B LI-B LOSW-B LO-B LG-C LI-C LOSW-C LO-C LG-D LI-D LOSW-D LO-D GPO0 GPO1 GPO2 GPO3 RESET 4LO- 4LO+ GAIN- GAIN+ Description Clock Input Complement. Clock Input True. 1.8 V Digital Output Driver Supply. ADC H Digital Output Complement. ADC H Digital Output True. ADC G Digital Output Complement. ADC G Digital Output True. ADC F Digital Output Complement. ADC F Digital Output True. ADC E Digital Output Complement. ADC E Digital Output True. Digital Clock Output Complement. Digital Clock Output True. Digital Frame Clock Output Complement. Digital Frame Clock Output True. ADC D Digital Output Complement. ADC D Digital Output True. ADC C Digital Output Complement. ADC C Digital Output True. ADC B Digital Output Complement. ADC B Digital Output True. ADC A Digital Output Complement. ADC A Digital Output True. Standby Power-Down. Full Power-Down. Serial Clock. Serial Data Input/Output. Chip Select Bar. LNA Ground for Channel A. LNA Analog Input for Channel A. LNA Analog Switched Output for Channel A. LNA Analog Inverted Output for Channel A. LNA Ground for Channel B. LNA Analog Input for Channel B. LNA Analog Switched Output for Channel B. LNA Analog Inverted Output for Channel B. LNA Ground for Channel C. LNA Analog Input for Channel C. LNA Analog Switched Output for Channel C. LNA Analog Inverted Output for Channel C. LNA Ground for Channel D. LNA Analog Input for Channel D. LNA Analog Switched Output for Channel D. LNA Analog Inverted Output for Channel D. General-Purpose Open-Drain Output 0. General-Purpose Open-Drain Output 1. General-Purpose Open-Drain Output 2. General-Purpose Open-Drain Output 3. Reset for Synchronizing 4LO Divide-by-4 Counter. CW Doppler 4LO Input Complement. CW Doppler 4LO Input True. Gain Control Voltage Input Complement. Gain Control Voltage Input True.
Rev. 0 | Page 12 of 48
AD9276
Pin No. 89 90 92 93 94 95 99 100 Name RBIAS VREF CWI- CWI+ CWQ- CWQ+ LO-E LOSW-E Description External Resistor to Set the Internal ADC Core Bias Current. Voltage Reference Input/Output. CW Doppler I Output Complement. CW Doppler I Output True. CW Doppler Q Output Complement. CW Doppler Q Output True. LNA Analog Inverted Output for Channel E. LNA Analog Switched Output for Channel E.
Rev. 0 | Page 13 of 48
AD9276 TYPICAL PERFORMANCE CHARACTERISTICS
TGC MODE
fSAMPLE = 40 MSPS, fIN = 5 MHz, RS = 50 , LNA gain = 21.3 dB, LNA bias = high, PGA gain = 27 dB, AAF LPF cutoff = fSAMPLE/3, HPF cutoff = LPF cutoff/20.7 (default).
2.0 1.5 1.0
GAIN ERROR (dB)
25
0.5 0 -0.5 -1.0 -1.5
-40C +25C +85C
PERCENTAGE OF UNITS (%)
08180-005
20
15
10
5
GAIN ERROR (dB)
Figure 5. Gain Error vs. GAIN+ at Three Temperatures
25
Figure 8. Gain Error Histogram, GAIN+ = 1.44 V
25
PERCENTAGE OF UNITS (%)
15
PERCENTAGE OF UNITS (%)
20
20
15
10
10
5
5
08180-006
-1.25 -1.00 -0.75 -0.50 -0.25
0
0.25 0.50 0.75 1.00 1.25
GAIN ERROR (dB)
CHANNEL-TO-CHANNEL GAIN MATCHING (dB)
Figure 6. Gain Error Histogram, GAIN+ = 0.16 V
14 12
Figure 9. Gain Match Histogram, GAIN+ = 0.3 V
25
PERCENTAGE OF UNITS (%)
10 8 6 4 2 0
PERCENTAGE OF UNITS (%)
20
15
10
5
08180-007
-1.25 -1.00 -0.75 -0.50 -0.25
0
0.25 0.50 0.75 1.00 1.25
GAIN ERROR (dB)
CHANNEL-TO-CHANNEL GAIN MATCHING (dB)
Figure 7. Gain Error Histogram, GAIN+ = 0.8 V
Rev. 0 | Page 14 of 48
Figure 10. Gain Match Histogram, GAIN+ = 1.3 V
08180-010
0
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
08180-009
0
0
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
08180-008
0
0.2
0.4
0.6
0.8 1.0 GAIN+ (V)
1.2
1.4
1.6
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
-2.0
0
AD9276
500k
-126
OUTPUT-REFERRED NOISE (dBFS/Hz)
450k 400k
NUMBER OF HITS
-128 -130 -132 -134 -136 -138 -140 LNA GAIN = 21.3dB
350k 300k 250k 200k 150k 100k 50k
08180-011
LNA GAIN = 17.9dB LNA GAIN = 15.6dB
-6
-5
-4
-3 -2
-1
0 1 CODES
2
3
4
5
6
7
0
0.2
0.4
0.6
0.8 GAIN+ (V)
1.0
1.2
1.4
1.6
Figure 11. Output-Referred Noise Histogram, GAIN+ = 0.0 V
Figure 14. Short-Circuit, Output-Referred Noise vs. GAIN+
180k 160k 140k
64 62 60 SNR
SNR/SINAD (dBFS)
NUMBER OF HITS
120k 100k 80k 60k 40k 20k
08180-012
58 56 54 52 50 0.4
SINAD
-4 -3
-2
-1
0 1 CODES
2
3
4
5
6
7
0.5
0.6
0.7
0.8
0.9 1.0 1.1 GAIN+ (V)
1.2
1.3
1.4
1.5 1.6
Figure 12. Output-Referred Noise Histogram, GAIN+ = 1.6 V
Figure 15. SNR/SINAD vs. GAIN+, AIN = -1.0 dBFS
2.0 1.8
INPUT-REFERRED NOISE (nV/ Hz)
0 MODE III - 80MSPS -5 MODE II - 65MSPS
1.6
1.2 1.0 0.8 0.6 0.4 0.2
08180-013
AMPLITUDE (dBFS)
1.4
LNA GAIN = 15.6dB LNA GAIN = 17.9dB
-10 MODE I - 40MSPS -15
LNA GAIN = 21.3dB
-20
1
2
3
4
5 6 7 FREQUENCY (MHz)
8
9
10
0
5
10
15 20 25 FREQUENCY (MHz)
30
35
40
Figure 13. Short-Circuit, Input-Referred Noise vs. Frequency, PGA Gain = 30 dB, GAIN+ = 1.6 V
Figure 16. Antialiasing Filter (AAF) Pass-Band Response, LPF Cutoff = fSAMPLE/3 (Mode I and Mode II), fSAMPLE/4.5 (Mode III)
Rev. 0 | Page 15 of 48
08180-016
0
-25
08180-015
0 -7 -6 -5
08180-014
0 -7
AD9276
SECOND-ORDER HARMONIC DISTORTION (dBFS)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 0 2 4 6 8 10 12 INPUT FREQUENCY (MHz) 14 16 GAIN+ = 1.0V GAIN+ = 1.6V GAIN+ = 0.4V
0
THIRD-ORDER HARMONIC DISTORTION (dBFS)
-20
-40 GAIN+ = 1.6V
-60
GAIN+ = 0V
-80 GAIN+ = 0.8V -100
08180-018
-35
-30
-25 -20 -15 -10 ADC OUTPUT LEVEL (dBFS)
-5
0
Figure 17. Second-Order Harmonic Distortion vs. Frequency, AIN = -1.0 dBFS
Figure 20. Third-Order Harmonic Distortion vs. ADC Output Level
0
THIRD-ORDER HARMONIC DISTORTION (dBFS)
0 -10 -20 -30
-10 -20 -30 -40 -50 -60 -70 -80 GAIN+ = 0.4V GAIN+ = 1.6V
fIN2 = fIN1 + 0.01MHz fIN1 = -1dBFS, fIN2 = -21dBFS
IMD3 (dBFS)
-40 -50 -60 -70 8MHz 2.3MHz 5MHz
GAIN+ = 1.0V
08180-019
-80
08180-022
08180-023
0
2
4
6 8 10 12 INPUT FREQUENCY (MHz)
14
16
-90
0.4
0.6
0.8
1.0 GAIN+ (V)
1.2
1.4
1.6
Figure 18. Third-Order Harmonic Distortion vs. Frequency, AIN = -1.0 dBFS
Figure 21. IMD3 vs. GAIN+
SECOND-ORDER HARMONIC DISTORTION (dBFS)
0
0
fIN1 = 5.00MHz, fIN2 = 5.01MHz FUND2 LEVEL = FUND1 LEVEL - 20dB
-20
-20
-40 GAIN+ = 0.8V -60 GAIN+ = 0V -80 GAIN+ = 1.6V -100
-40
IMD3 (dBFS)
-60 GAIN+ = 0V -80 GAIN+ = 1.6V
-100 GAIN+ = 0.8V
08180-020
-120 -50
-40
-30 -20 ADC OUTPUT LEVEL (dBFS)
-10
0
-120 -40
-35
-30
-25 -20 -15 -10 AMPLITUDE LEVEL (dBFS)
-5
0
Figure 19. Second-Order Harmonic Distortion vs. ADC Output Level
Figure 22. IMD3 vs. Amplitude Level
Rev. 0 | Page 16 of 48
08180-021
-120 -40
AD9276
CW DOPPLER MODE
fRF = 2.5 MHz at -3 dBFS, f4LO = 10 MHz, RS = 50 , LNA gain = 21.3 dB, LNA bias = high, all CW channels enabled, phase rotation 0.
1.2
QUADRATURE PHASE ERROR (Degrees)
175
1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
08180-073
170
CH A + B + C + D + E + F + G + H CH A + B + C + D
DYNAMIC RANGE (dBFS/ Hz)
165 CH A 160
CH A + B
155
150
1k 10k BASEBAND FREQUENCY (Hz)
0
1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000 BASEBAND FREQUENCY (Hz)
Figure 23. Quadrature Phase Error vs. Baseband Frequency
Figure 26. Small-Signal Dynamic Range
0.10
QUADRATURE AMPLITUDE IMBALANCE (dB)
12
0.08 0.06
NOISE FIGURE (dB)
10
0.04 0.02 0 -0.02 -0.04 -0.06 -0.08
08180-074
8
6
4
2
1k 10k BASEBAND FREQUENCY (Hz)
0
1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000 BASEBAND FREQUENCY (Hz)
Figure 24. Quadrature Amplitude Imbalance vs. Baseband Frequency
Figure 27. Noise Figure vs. Baseband Frequency
140 142
OUTPUT-REFERRED SNR (dBc/ Hz) OUTPUT-REFERRED SNR (dBc/ Hz)
130 135 140 145 150 155 160 165
144 146 148 150 152 154 156 158 160 162 164
08180-075
1kHz OFFSET 5kHz OFFSET
-18
-16
-14
-12 -10 -8 -6 INPUT LEVEL (dBFS)
-4
-2
0
0
1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000 BASEBAND FREQUENCY (Hz)
Figure 25. Output-Referred SNR vs. Input Level
Figure 28. Output-Referred SNR vs. Baseband Frequency
Rev. 0 | Page 17 of 48
08180-078
166 -20
08180-077
-0.10 100
0
08180-076
-1.2 100
145
AD9276
170 168 166 LNA GAIN = 15.6dB LNA GAIN = 17.9dB
DYNAMIC RANGE (dB)
164 162 160 158 156
LNA GAIN = 21.3dB
1
2
3 4 5 RF FREQUENCY (MHz)
6
7
8
9 10
Figure 29. Small-Signal Dynamic Range vs. RF Frequency
08180-079
154
Rev. 0 | Page 18 of 48
AD9276 EQUIVALENT CIRCUITS
AVDD2 VCM 15k LI-x, LG-x
08180-024
AVDD1
SDIO
350
Figure 30. Equivalent LNA Input Circuit
Figure 34. Equivalent SDIO Input Circuit
DRVDD
AVDD2 AVDD2
DRVDD
DRVDD
V
LO-x, LOSW-x 10
V DOUTx+
DOUTx- V
08180-025
V
08180-028
30k
DRGND
Figure 31. Equivalent LNA Output Circuit
Figure 35. Equivalent Digital Output Circuit
AVDD1
CLK+
350
AVDD1
10k 1.25V AVDD1 10k 350
SCLK, PDWN, OR STBY
350 30k
08180-030
CLK-
08180-026
Figure 32. Equivalent Clock Input Circuit
Figure 36. Equivalent SCLK, PDWN, or STBY Input Circuit
AVDD2
4LO+
350
AVDD2
10k 1.25V AVDD2 10k 350
RESET
350
4LO-
Figure 33. Equivalent 4LO Input Circuit
08180-027
Figure 37. Equivalent RESET Input Circuit
Rev. 0 | Page 19 of 48
08180-031
08180-029
AD9276
AVDD1 AVDD1 350 70k GAIN+ AVDD2
CSB
50
Figure 38. Equivalent CSB Input Circuit
08180-033
Figure 41. Equivalent GAIN+ Input Circuit
AVDD2
VREF 6k
08180-034
0.8V 70k
GAIN-
50
08180-035
Figure 39. Equivalent VREF Circuit
Figure 42. Equivalent GAIN- Input Circuit
AVDD2
Figure 43. Equivalent CWI, CWQ Output Circuit
08180-032
AVDD2
Figure 40. Equivalent RBIAS Circuit
GPOx 10
08180-038
Figure 44. Equivalent GPOx Output Circuit
Rev. 0 | Page 20 of 48
08180-037
RBIAS
100
CWx+, CWx-
08180-036
AD9276 THEORY OF OPERATION
ULTRASOUND
The primary application for the AD9276 is medical ultrasound. Figure 45 shows a simplified block diagram of an ultrasound system. A critical function of an ultrasound system is the time gain control (TGC) compensation for physiological signal attenuation. Because the attenuation of ultrasound signals is exponential with respect to distance (time), a linear-in-dB VGA is the optimal solution. Key requirements in an ultrasound signal chain are very low noise, active input termination, fast overload recovery, low power, and differential drive to an ADC. Because ultrasound machines use beamforming techniques requiring large binary-weighted numbers of channels (for example, 32 to 512), using the lowest power at the lowest possible noise is of chief importance. Most modern ultrasound machines use digital beamforming. In this technique, the signal is converted to digital format immediately following the TGC amplifier, and then beamforming is accomplished digitally. The ADC resolution of 12 bits with up to 80 MSPS sampling satisfies the requirements of both general-purpose and high end systems. Power conservation and low cost are two of the most important factors in low end and portable ultrasound machines, and the AD9276 is designed to meet these criteria. For additional information regarding ultrasound systems, refer to "How Ultrasound System Considerations Influence Front-End Component Choice," Analog Dialogue, Volume 36, Number 3, May-July 2002, and "The AD9271--A Revolutionary Solution for Portable Ultrasound," Analog Dialogue, Volume 41, Number 7, July 2007.
Tx HV AMPLIFIERS
Tx BEAMFORMER
BEAMFORMER CENTRAL CONTROL
MULTICHANNELS HV MUX/ DEMUX
T/R SWITCHES
LNA
VGA AAF
ADC
Rx BEAMFORMER (B AND F MODES)
TRANSDUCER ARRAY 128, 256, ETC., ELEMENTS BIDIRECTIONAL CABLE
CW (ANALOG) BEAMFORMER
SPECTRAL DOPPLER PROCESSING MODE
IMAGE AND MOTION PROCESSING (B MODE)
COLOR DOPPLER (PW) PROCESSING (F MODE)
Figure 45. Simplified Ultrasound System Block Diagram
Rev. 0 | Page 21 of 48
08180-039
AUDIO OUTPUT
DISPLAY
AD9276
4LO- 4LO+ RESET RFB1 RFB2 T/R SWITCH C S CSH CLG TRANSDUCER LO-x LOSW-x LI-x LG-x LNA 15.6dB, 17.9dB, 21.3dB LO GENERATION 4 CWI+ CWI- CWQ+ CWQ-
ATTENUATOR -42dB TO 0dB
POST AMP 21dB, 24dB, 27dB, 30dB
AAF
PIPELINE ADC
SERIAL LVDS
DOUTx+ DOUTx-
GAIN INTERPOLATOR
X-AMP VGA
08180-040
GAIN+
GAIN-
Figure 46. Simplified Block Diagram of a Single Channel
CHANNEL OVERVIEW
Each channel contains both a TGC signal path and a CW Doppler signal path. Common to both signal paths, the LNA provides useradjustable input impedance termination. The CW Doppler path includes an I/Q demodulator. The TGC path includes a differential X-AMP(R) VGA, an antialiasing filter, and an ADC. Figure 46 shows a simplified block diagram with external components. The signal path is fully differential throughout to maximize signal swing and reduce even-order distortion; however, the LNA is designed to be driven from a single-ended signal source.
T/R SWITCH CS CSH TRANSDUCER VO+
CFB
RFB1 RFB2 VO- LOSW-x LO-x
VCM
VCM
LI-x
LG-x
CLG
Low Noise Amplifier (LNA)
Good noise performance relies on a proprietary ultralow noise LNA at the beginning of the signal chain, which minimizes the noise contribution in the following VGA. Active impedance control optimizes noise performance for applications that benefit from input impedance matching. A simplified schematic of the LNA is shown in Figure 47. LI-x is capacitively coupled to the source. An on-chip bias generator establishes dc input bias voltages of around 0.9 V and centers the output common-mode levels at 1.5 V (AVDD2 divided by 2). A capacitor, CLG, of the same value as the input coupling capacitor, CS, is connected from the LG-x pin to ground. It is highly recommended that the LG-x pins form a Kelvin type connection to the input or probe connection ground. Simply connecting the LG-x pin to ground near the device can allow differences in potential to be amplified through the LNA. This generally shows up as a dc offset voltage that can vary from channel to channel and part to part, depending on the application and the layout of the PCB.
Figure 47. Simplified LNA Schematic
The LNA supports differential output voltages as high as 4.4 V p-p with positive and negative excursions of 1.1 V from a commonmode voltage of 1.5 V. The LNA differential gain sets the maximum input signal before saturation. One of three gains is set through the SPI. The corresponding full-scale input for the gain settings of 15.6 dB, 17.9 dB, and 21.3 dB is 733 mV p-p, 550 mV p-p, and 367 mV p-p, respectively. Overload protection ensures quick recovery time from large input voltages. Because the inputs are capacitively coupled to a bias voltage near midsupply, very large inputs can be handled without interacting with the ESD protection.
Rev. 0 | Page 22 of 48
08180-041
AD9276
Low value feedback resistors and the current-driving capability of the output stage allow the LNA to achieve a low inputreferred noise voltage of 0.75 nV/Hz (at a gain of 21.3 dB). This is achieved with a current consumption of only 27 mA per channel (80 mW). On-chip resistor matching results in precise single-ended gains, which are critical for accurate impedance control. The use of a fully differential topology and negative feedback minimizes distortion. Low second-order harmonic distortion is particularly important in second harmonic ultrasound imaging applications. Differential signaling enables smaller swings at each output, further reducing third-order harmonic distortion. The bandwidth (BW) of the LNA is greater than 100 MHz. Ultimately, the BW of the LNA limits the accuracy of the synthesized RIN. For RIN = RS up to about 200 , the best match is between 100 kHz and 10 MHz, where the lower frequency limit is determined by the size of the ac coupling capacitors, and the upper limit is determined by the LNA BW. Furthermore, the input capacitance and RS limit the BW at higher frequencies. Figure 48 shows RIN vs. frequency for various values of RFB.
1k RS = 500, RFB = 2k
INPUT RESISTANCE ()
Active Impedance Matching
The LNA consists of a single-ended voltage gain amplifier with differential outputs and the negative output externally available. For example, with a fixed gain of 8x (17.9 dB), an active input termination is synthesized by connecting a feedback resistor between the negative output pin, LO-x, and the positive input pin, LI-x. This well-known technique is used for interfacing multiple probe impedances to a single system. The input resistance is shown in Equation 1.
R IN = R FB (1 + A 2)
RS = 200, RFB = 800 RS = 100, RFB = 400, CSH = 20pF RS = 50, RFB = 200, CSH = 70pF
100
1M
10M
100M
FREQUENCY (Hz)
(1)
Figure 48. RIN vs. Frequency for Various Values of RFB (Effects of RS and CSH Are Also Shown)
where: A/2 is the single-ended gain or the gain from the LI-x inputs to the LO-x outputs. RFB is the resulting impedance of the RFB1 and RFB2 combination (see Figure 47). Because the amplifier has a gain of 8x from its input to its differential output, it is important to note that the gain A/2 is the gain from Pin LI-x to Pin LO-x and that it is 6 dB less than the gain of the amplifier, or 11.9 dB (4x). The input resistance is reduced by an internal bias resistor of 15 k in parallel with the source resistance connected to Pin LI-x, with Pin LG-x ac grounded. Equation 2 can be used to calculate the required RFB for a desired RIN, even for higher values of RIN.
R IN R = FB || 15 k (1 + 3)
Note that at the lowest value of RIN (50 ), RIN peaks at frequencies greater than 10 MHz. This is due to the BW roll-off of the LNA, as mentioned previously. However, as can be seen for larger RIN values, parasitic capacitance starts rolling off the signal BW before the LNA can produce peaking. CSH further degrades the match; therefore, CSH should not be used for values of RIN that are greater than 100 . Table 7 lists the recommended values for RFB and CSH in terms of RIN. CFB is needed in series with RFB because the dc levels at Pin LO-x and Pin LI-x are unequal. Table 7. Active Termination External Component Values
LNA Gain (dB) 15.6 17.9 21.3 15.6 17.9 21.3 15.6 17.9 21.3 RIN () 50 50 50 100 100 100 200 200 200 RFB () 200 250 350 400 500 700 800 1000 1400 Minimum CSH (pF) 90 70 50 30 20 10 N/A N/A N/A BW (MHz) 57 69 88 57 69 88 72 72 72
(2)
For example, to set RIN to 200 , the value of RFB must be 1000 . If the simplified equation (Equation 2) is used to calculate RIN, the value is 188 , resulting in a gain error of less than 0.6 dB. Some factors, such as the presence of a dynamic source resistance, may influence the absolute gain accuracy more significantly. At higher frequencies, the input capacitance of the LNA must be considered. The user must determine the level of matching accuracy and adjust RFB accordingly.
Rev. 0 | Page 23 of 48
08180-042
10 100k
AD9276
LNA Noise
The short-circuit noise voltage (input-referred noise) is an important limit on system performance. The short-circuit noise voltage for the LNA is 0.75 nV/Hz at a gain of 21.3 dB, including the VGA noise at a VGA postamp gain of 27 dB. These measurements, which were taken without a feedback resistor, provide the basis for calculating the input noise and noise figure (NF) performance of the configurations shown in Figure 49.
RS LI-x + - RESISTIVE TERMINATION RS LI-x + - RIN RS
NOISE FIGURE (dB)
Figure 50 shows the relative noise figure performance. With an LNA gain of 21.3 dB, the input impedance was swept with RS to preserve the match at each point. The noise figures for a source impedance of 50 are 7.3 dB, 4.2 dB, and 2.8 dB for the resistive termination, active termination, and unterminated configurations, respectively. The noise figures for 200 are 4.5 dB, 1.7 dB, and 1.0 dB, respectively. Figure 51 shows the noise figure as it relates to RS for various values of RIN, which is helpful for design purposes.
12.0 10.5 9.0 7.5 6.0 4.5 3.0 ACTIVE TERMINATION UNTERMINATED 1.5
08180-044
UNTERMINATED RIN
VOUT
RESISTIVE TERMINATION
VOUT
ACTIVE IMPEDANCE MATCH RFB R RS LI-x + - RFB 1 + A/2
08180-043
IN
0
VOUT
10
100 RS ()
1k
Figure 50. Noise Figure vs. RS for Resistive Termination, Active Termination Matched, and Unterminated Inputs, VGAIN = 0.8 V
RIN =
Figure 49. Input Configurations
8 7 6
NOISE FIGURE (dB)
Figure 50 and Figure 51 are simulations of noise figure vs. RS results using these configurations and an input-referred noise voltage of 3.8 nV/Hz for the VGA. Unterminated (RFB = ) operation exhibits the lowest equivalent input noise and noise figure. Figure 51 shows the noise figure vs. source resistance rising at low RS--where the LNA voltage noise is large compared with the source noise--and at high RS due to the noise contribution from RFB. The lowest NF is achieved when RS matches RIN. The main purpose of input impedance matching is to improve the transient response of the system. With resistive termination, the input noise increases due to the thermal noise of the matching resistor and the increased contribution of the LNA's input voltage noise generator. With active impedance matching, however, the contributions of both are smaller (by a factor of 1/(1 + LNA gain)) than they would be for resistive termination.
RIN = 50 RIN = 75 RIN = 100 RIN = 200 UNTERMINATED
5 4 3 2 1
08180-045
0
10
100 RS ()
1k
Figure 51. Noise Figure vs. RS for Various Fixed Values of RIN, Active Termination Matched Inputs, VGAIN = 0.8 V
Rev. 0 | Page 24 of 48
AD9276
INPUT OVERDRIVE
Excellent overload behavior is of primary importance in ultrasound. Both the LNA and VGA have built-in overdrive protection and quickly recover after an overload event.
CW DOPPLER OPERATION
Each channel of the AD9276 includes an I/Q demodulator. Each demodulator has an individual programmable phase shifter. The I/Q demodulator is ideal for phased array beamforming applications in medical ultrasound. Each channel can be programmed for 16 delay states (360/16 or 22.5/step), selectable via the SPI port. The part has a RESET input used to synchronize the LO dividers of each channel. If multiple AD9276s are used, a common RESET across the array ensures synchronized phase for all channels. Internal to the AD9276, the individual channel I and Q outputs are current summed. If multiple AD9276s are used, the I and Q outputs from each AD9276 can be current summed and converted to a voltage using an external transimpedance amplifier.
Input Overload Protection
As with any amplifier, voltage clamping prior to the inputs is highly recommended if the application is subject to high transient voltages. Figure 52 shows a simplified ultrasound transducer interface. A common transducer element serves the dual functions of transmitting and receiving ultrasound energy. During the transmitting phase, high voltage pulses are applied to the ceramic elements. A typical transmit/receive (T/R) switch can consist of four high voltage diodes in a bridge configuration. Although the diodes ideally block transmit pulses from the sensitive receiver input, diode characteristics are not ideal, and the resulting leakage transients imposed on the LI-x inputs can be problematic. Because ultrasound is a pulse system and time-of-flight is used to determine depth, quick recovery from input overloads is essential. Overload can occur in the preamplifier and in the VGA. Immediately following a transmit pulse, the typical VGA gains are low, and the LNA is subject to overload from T/R switch leakage. With increasing gain, the VGA can become overloaded due to strong echoes that occur near field echoes and acoustically dense materials, such as bone. Figure 52 illustrates an external overload protection scheme. A pair of back-to-back signal diodes should be in place prior to the ac coupling capacitors. Keep in mind that all diodes are prone to exhibiting some amount of shot noise. Many types of diodes are available for achieving the desired noise performance. The configuration shown in Figure 52 tends to add 2 nV/Hz of input-referred noise. Decreasing the 5 k resistor and increasing the 2 k resistor may improve noise contribution, depending on the application. With the diodes shown in Figure 52, clamping levels of 0.5 V or less significantly enhance the overload performance of the system.
+5V Tx DRIVER 5k
Quadrature Generation
The internal 0 and 90 LO phases are digitally generated by a divide-by-4 logic circuit. The divider is dc-coupled and inherently broadband; the maximum LO frequency is limited only by its switching speed. The duty cycle of the quadrature LO signals is intrinsically 50% and is unaffected by the asymmetry of the externally connected 4LO input. Furthermore, the divider is implemented such that the 4LO signal reclocks the final flipflops that generate the internal LO signals and thereby minimizes noise introduced by the divide circuitry. For optimum performance, the 4LO input is driven differentially, as done on the AD9276 evaluation board. The common-mode voltage on each pin is approximately 1.2 V with the nominal 3 V supply. It is important to ensure that the LO source has very low phase noise (jitter), fast slew rate, and adequate input level to obtain optimum performance of the CW signal chain. Beamforming applications require a precise channel-to-channel phase relationship for coherence among multiple channels. A RESET pin is provided to synchronize the LO divider circuits in different AD9276s when they are used in arrays. The RESET pin resets the dividers to a known state after power is applied to multiple AD9276s. Accurate channel-to-channel phase matching can only be achieved via a common pulse on the RESET pin when using more than one AD9276.
HV 10nF
AD9276
LNA
TRANSDUCER -5V
Figure 52. Input Overload Protection
Rev. 0 | Page 25 of 48
08180-046
5k
2k
10nF
AD9276
I/Q Demodulator and Phase Shifter
The I/Q demodulators consist of double-balanced passive mixers. The RF input signals are converted into currents by transconductance stages that have a maximum differential input signal capability matching the LNA output full scale. These currents are then presented to the mixers, which convert them to baseband (RF - LO) and twice RF (RF + LO). The signals are phase shifted according to the codes programmed into the SPI latch (see Table 8). The phase shift function is an integral part of the overall circuit. The phase shift listed in Column 1 of Table 8 is defined as being between the baseband I or Q channel outputs. As an example, for a common signal applied to a pair of RF inputs to an AD9276, the baseband outputs are in phase for matching phase codes. However, if the phase code for Channel 1 is 0000 and that of Channel 2 is 0001, then Channel 2 leads Channel 1 by 22.5. Table 8. Phase Select Code for Channel-to-Channel Phase Shift
Shift 0 22.5 45 67.5 90 112.5 135 157.5 180 202.5 225 247.5 270 292.5 315 337.5 I/Q Demodulator Phase (SPI Register 0x2D[3:0]) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Dynamic Range and Noise
Figure 53 is an interconnection block diagram of all eight channels of the AD9276. More channels are easily added to the summation (up to 32 when using an AD8021 as the summation amplifier) by wire-OR connecting the outputs as shown. In beamforming applications, the I and Q outputs of a number of receiver channels are summed. The dynamic range of the system increases by the factor 10 log10(N), where N is the number of channels (assuming random uncorrelated noise). The noise in the 8-channel example of Figure 53 is increased by 9 dB, whereas the signal quadruples (18 dB), yielding an aggregate SNR improvement of (18 - 9) = 9 dB. The output-referred noise of the CW signal path depends on the LNA gain, the selection of the external summing amplifier, and the value of RFILT. To determine the output-referred noise, it is important to know the active low-pass filter (LPF) values, RFILT and CFILT, shown in Figure 53. Typical filter values for a single channel are 2 k for RFILT and 0.8 nF for CFILT; these values implement a 100 kHz single-pole LPF. In the case where eight channels are summed, RFILT and CFILT are 250 and 6.4 nF. If the RF and LO are offset by 10 kHz, the demodulated signal is 10 kHz and is passed by the LPF. The single-channel mixing gain from the RF input to the AD8021 output (for example, I1, Q1) is approximately the LNA gain for RFILT and CFILT of 2 k and 0.8 nF. This gain can be increased by increasing the filter resistor while maintaining the corner frequency. The factor limiting the magnitude of the gain is the output swing and drive capability of the op amp selected for the I-to-V converter, in this example, the AD8021. Because any amplifier has limited drive capability, there is a finite number of channels that can be summed. The channel-summing limit relates directly to the current drive capability of the amplifier used to implement the active lowpass filter and current-to-voltage converter. The maximum sum, when the AD8021 is used, is 32 channels of the AD9276; that is, four AD9276s (4 x 8 = 32 channels) can be summed in one AD8021.
Rev. 0 | Page 26 of 48
AD9276
CFILT OTHER
AD9276s
CWI+
RFILT
AD8021
CHANNEL A
LNA
1.5V
I
1.5V CWI- AD8021 RFILT CFILT CFILT RFILT CWQ+ AD8021 1.5V
18-BIT ADC
Q
1.5V
18-BIT ADC
CHANNEL H
LNA
CWQ-
AD8021 RFILT CFILT
4 LO GENERATION
RESET
4LO+
4LO-
Figure 53. Typical Connection Interface for I/Q Outputs in CW Mode
Phase Compensation and Analog Beamforming
Beamforming, as applied to medical ultrasound, is defined as the phase alignment and summation of signals generated from a common source but received at different times by a multielement ultrasound transducer. Beamforming has two functions: it imparts directivity to the transducer, enhancing its gain, and it defines a focal point within the body from which the location of the returning echo is derived. The primary application for the AD9276 I/Q demodulators is in analog beamforming circuits for ultrasound CW Doppler. Modern ultrasound machines used for medical applications employ an array of receivers for beamforming, with typical CW Doppler array sizes of up to 64 receiver channels that are phase shifted and summed together to extract coherent information. When used in multiples, the desired signals from each of the channels can be summed to yield a larger signal (increased by a factor N, where N is the number of channels), whereas the noise is increased by the square root of the number of channels. This technique enhances the signal-to-noise performance of the machine. The critical elements in a beamformer design are the means to align the incoming signals in the time domain and the means to sum the individual signals into a composite whole.
In traditional analog beamformers incorporating Doppler, a V-to-I converter per channel and a crosspoint switch precede passive delay lines used as a combined phase shifter and summing circuit. The system operates at the carrier frequency (RF) through the delay line, which also sums the signals from the various channels, and then the combined signal is downconverted by an I/Q demodulator. The dynamic range of the demodulator can limit the achievable dynamic range. The resultant I and Q signals are filtered and then sampled by two high resolution analog-to-digital converters. The sampled signals are processed to extract the relevant Doppler information. Alternatively, the RF signal can be processed by downconversion on each channel individually, phase shifting the downconverted signal and then combining all channels. Because the dynamic range expansion from beamforming occurs after demodulation, the demodulator dynamic range has little effect on the output dynamic range. The AD9276 implements this architecture. The downconversion is done by an I/Q demodulator on each channel, and the summed current output is the same as in the delay line approach. The subsequent filters after the I-to-V conversion and the ADCs are similar.
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08180-047
AD9276
For CW Doppler operation, the AD9276 integrates the LNA, phase shifter, frequency conversion, and I/Q demodulation into a single package and directly yields the baseband signal. Figure 54 is a simplified diagram showing the concept for four channels. The ultrasound wave (US wave) is received by four transducer elements, TE1 through TE4, in an ultrasound probe and generates signals E1 through E4. In this example, the phase at TE1 leads the phase at TE2 by 45. In a real application, the phase difference depends on the element spacing, wavelength (), speed of sound, angle of incidence, and other factors. In Figure 54, the signals E1 through E4 are amplified by the low noise amplifiers. For optimum signal-to-noise performance, the output of the LNA is applied directly to the input of the demodulators. To sum the signals E1 through E4, E2 is shifted 45 relative to E1 by setting the phase code in Channel 2 to 0010, E3 is shifted 90 (0100), and E4 is shifted 135 (0110). The phase-aligned current signals at the output of the AD9276 are summed in an I-to-V converter to provide the combined output signal with a theoretical improvement in dynamic range of 6 dB for the four channels. The RESET mechanism also allows the measurement of nonmixing gain from the RF input to the output. The rising edge of the active high RESET pulse can occur at any time; however, the duration should be 20 ns minimum. When the RESET pulse transitions from high to low, the LO dividers are reactivated on the next rising edge of the 4LO clock. To guarantee synchronous operation of multiple AD9276s, the RESET pulse must go low on all devices before the next rising edge of the 4LO clock. Therefore, it is best to have the RESET pulse go low on the falling edge of the 4LO clock; at the very least, the tSETUP should be 5 ns. An optimal timing setup is for the RESET pulse to go high on a 4LO falling edge and to go low on a 4LO falling edge; this gives 15 ns of setup time even at a 4LO frequency of 32 MHz (8 MHz internal LO). Check the synchronization of multiple AD9276s using the following procedure: 1. Activate at least one channel per AD9276 by setting the appropriate channel enable bit in the serial interface (see Table 18, Register 0x2D, Bit 4). Set the phase code of all AD9276 channels to the same logic state, for example, 0000. Apply the same test signal to all devices to generate a sine wave in the baseband output and measure the output of one channel per device. Apply a RESET pulse to all AD9276s. Because all the phase codes of the AD9276s should be the same, the combined signal of multiple devices should be N times greater than a single channel. If the combined signal is less than N times one channel, one or more of the LO phases of the individual AD9276s is in error.
CW Application Information
The RESET pin is used to synchronize the LO dividers when using multiple AD9276s. Because they are driven by the same internal LO, the channels in any AD9276 are inherently synchronous. However, when multiple AD9276s are used, it is possible for their dividers to wake up in different phase states. The function of the RESET pin is to phase align all the LO signals in multiple AD9276s. The 4LO divider of each AD9276 can be initiated in one of four possible states: 0, 90, 180, and 270 relative to other AD9276s. The internally generated I/Q signals of each AD9276 LO are always at a 90 angle relative to each other, but a phase shift can occur during power-up between the dividers of multiple AD9276s used in a common array.
TRANSDUCER ELEMENTS TE1 THROUGH TE4 CONVERT US TO ELECTRICAL SIGNALS E1 LNA 0 E2 4 US WAVES ARE DELAYED 45 EACH WITH RESPECT TO EACH OTHER LNA 45 90 135 E3 LNA
2. 3.
4. 5.
PHASE BIT SETTINGS CH 1 PHASE SET FOR 135 LAG CH 2 PHASE SET FOR 90 LAG
S1 THROUGH S4 ARE NOW IN PHASE S1
S2
SUMMED OUTPUT S1 + S2 + S3 + S4
CH 3 PHASE SET FOR 45 LAG CH 4 PHASE SET FOR 0 LAG
S3
E4 LNA
S4
08180-048
Figure 54. Simplified Example of the AD9276 Phase Shifter
Rev. 0 | Page 28 of 48
AD9276
TGC OPERATION
The TGC signal path is fully differential throughout to maximize signal swing and reduce even-order distortion; however, the LNAs are designed to be driven from a single-ended signal source. Gain values are referenced from the single-ended LNA input to the differential ADC input. A simple exercise in understanding the maximum and minimum gain requirements is shown in Figure 55. The maximum gain required is determined by (ADC Noise Floor/LNA Input Noise Floor) + Margin = 20 log(224/3.9) + 11 dB = 46 dB The minimum gain required is determined by (ADC Input FS/LNA Input FS) + Margin = 20 log(2/0.55) - 10 dB = 3 dB Therefore, 42 dB of gain range for a 12-bit, 40 MSPS ADC with 15 MHz of bandwidth should suffice in achieving the dynamic range required for most of today's ultrasound systems. The system gain is distributed as listed in Table 9. Table 9. Channel Gain Distribution
Section LNA Attenuator VGA Amplifier Filter ADC Nominal Gain (dB) 15.6/17.9/21.3 -42 to 0 21/24/27/30 0 0
The linear-in-dB gain (law conformance) range of the TGC path is 42 dB. The slope of the gain control interface is 28.5 dB/V, and the gain control range is -0.8 V to +0.8 V. Equation 3 is the expression for the differential voltage VGAIN, and Equation 4 is the expression for the channel gain. VGAIN (V) = (GAIN+) - (GAIN-) Gain (dB) = 28.5 dB/V x VGAIN + ICPT where ICPT is the intercept point of the TGC gain. In its default condition, the LNA has a gain of 21.3 dB (12x), and the VGA postamp gain is 24 dB if the voltage on the GAIN+ pin is 0 V and the voltage on the GAIN- pin is 0.8 V (42 dB attenuation). This results in a total gain (or ICPT) of 3.6 dB through the TGC path if the LNA input is unmatched, or a total gain of -2.4 dB if the LNA is matched to 50 (RFB = 350 ). However, if the voltage on the GAIN+ pin is 1.6 V and the voltage on the GAIN- pin is 0.8 V (0 dB attenuation), the VGA gain is 24 dB. This results in a total gain of 45 dB through the TGC path if the LNA input is unmatched or in a total gain of 39 dB if the LNA input is matched. Each LNA output is dc-coupled to a VGA input. The VGA consists of an attenuator with a range of -42 dB to 0 dB followed by an amplifier with 21 dB/24 dB/27 dB/30 dB of gain. The X-AMP gain interpolation technique results in low gain error and uniform bandwidth, and differential signal paths minimize distortion. (3) (4)
MINIMUM GAIN LNA FULL SCALE (0.55V p-p SINGLE-ENDED) 94dB LNA 70dB
ADC FULL SCALE (2V p-p) ~10dB MARGIN ADC
>11dB MARGIN ADC NOISE FLOOR (224V rms) MAXIMUM GAIN
08180-049
LNA INPUT-REFERRED NOISE FLOOR (3.9V rms) @ AAF BW = 15MHz LNA + VGA NOISE = 1.0nV/ Hz
VGA GAIN RANGE > 42dB MAX CHANNEL GAIN > 48dB
Figure 55. Gain Requirements of TGC Operation for a 12-Bit, 40 MSPS ADC
Rev. 0 | Page 29 of 48
AD9276
Table 10. Sensitivity and Dynamic Range Trade-Offs 1, 2, 3
LNA Gain (V/V) 6 (dB) 15.6 Full-Scale Input (V p-p) 0.733 Input Noise (nV/Hz) 0.98 Postamp Gain (dB) 21 24 27 30 21 24 27 30 21 24 27 30 VGA Channel Typical Output Dynamic Range (dB) GAIN+ = 0 V 67.5 66.4 64.6 62.5 67.5 66.4 64.6 62.5 67.5 66.4 64.6 62.5
4
8
17.9
0.550
0.86
12
21.3
0.367
0.75
GAIN+ = 1.6 V 65.1 63.0 60.6 57.9 64.5 62.3 59.8 57.1 63.3 60.9 58.2 55.4
5
Input-Referred Noise 6 @ GAIN+ = 1.6 V (nV/Hz) 1.395 1.286 1.227 1.197 1.149 1.071 1.030 1.009 0.910 0.865 0.842 0.830
1 2
LNA: output full scale = 4.4 V p-p differential. Filter: loss 1 dB, NBW = 13.3 MHz, GAIN- = 0.8 V. 3 ADC: 40 MSPS, 70 dB SNR, 2 V p-p full-scale input. 4 Output dynamic range at minimum VGA gain (VGA dominated). 5 Output dynamic range at maximum VGA gain (LNA dominated). 6 Channel noise at maximum VGA gain.
Table 10 demonstrates the sensitivity and dynamic range trade-offs that can be achieved relative to various LNA and VGA gain settings. For example, when the VGA is set for the minimum gain voltage, the TGC path is dominated by VGA noise and achieves the maximum output SNR. However, as the postamp gain options are increased, the input-referred noise is reduced and the SNR is degraded. If the VGA is set for the maximum gain voltage, the TGC path is dominated by LNA noise and achieves the lowest inputreferred noise, but with degraded output SNR. The higher the TGC (LNA + VGA) gain, the lower the output SNR. As the postamp gain is increased, the input-referred noise is reduced. At low gains, the VGA should limit the system noise performance (SNR); at high gains, the noise is defined by the source and the LNA. The maximum voltage swing is bound by the full-scale peak-to-peak ADC input voltage (2 V p-p). Both the LNA and VGA have full-scale limitations within each section of the TGC path. These limitations are dependent on the gain setting of each function block and on the voltage applied to the GAIN+ and GAIN- pins. The LNA has three limitations, or full-scale settings, that can be applied through the SPI.
Similarly, the VGA has four postamp gain settings that can be applied through the SPI. The voltage applied to the GAIN pins determines which amplifier (the LNA or VGA) saturates first. The maximum signal input level that can be applied as a function of voltage on the GAIN pins for the selectable gain options of the SPI is shown in Figure 56 to Figure 58.
0.9 0.8
INPUT FULL SCALE (V p-p)
0.7 0.6 0.5 0.4 0.3 0.2 0.1 PGA GAIN = 27dB PGA GAIN = 30dB 0 0.2 0.4 0.6 0.8 1.0 GAIN+ (V) 1.2 1.4 1.6
08180-050
PGA GAIN = 21dB PGA GAIN = 24dB
0
Figure 56. LNA with 15.6 dB Gain Setting/VGA Full-Scale Limitations
Rev. 0 | Page 30 of 48
AD9276
0.6 0.5
INPUT FULL SCALE (V p-p)
PGA GAIN = 21dB
0.4 PGA GAIN = 24dB 0.3
0.2
0.1
PGA GAIN = 27dB PGA GAIN = 30dB 0 0.2 0.4 0.6 0.8 1.0 GAIN+ (V) 1.2 1.4 1.6
08180-051
0
The input of the VGA is a 14-stage differential resistor ladder with 3.5 dB per tap. The resulting total gain range is 42 dB, which allows for range loss at the endpoints. The effective input resistance per side is 180 nominally for a total differential resistance of 360 . The ladder is driven by a fully differential input signal from the LNA. LNA outputs are dc-coupled to avoid external decoupling capacitors. The common-mode voltage of the attenuator and the VGA is controlled by an amplifier that uses the same midsupply voltage derived in the LNA, permitting dc coupling of the LNA to the VGA without introducing large offsets due to commonmode differences. However, any offset from the LNA becomes amplified as the gain increases, producing an exponentially increasing VGA output offset. The input stages of the X-AMP are distributed along the ladder, and a biasing interpolator, controlled by the gain interface, determines the input tap point. With overlapping bias currents, signals from successive taps merge to provide a smooth attenuation range from -42 dB to 0 dB. This circuit technique results in linear-in-dB gain law conformance and low distortion levels--only deviating 0.5 dB or less from the ideal. The gain slope is monotonic with respect to the control voltage and is stable with variations in process, temperature, and supply. The X-AMP inputs are part of a programmable gain feedback amplifier that completes the VGA. Its bandwidth is approximately 100 MHz. The input stage is designed to reduce feedthrough to the output and to ensure excellent frequency response uniformity across the gain setting.
Figure 57. LNA with 17.9 dB Gain Setting/VGA Full-Scale Limitations
0.40 0.35 PGA GAIN = 21dB
INPUT FULL SCALE (V p-p)
0.30 PGA GAIN = 24dB 0.25 0.20 0.15 PGA GAIN = 27dB 0.10 PGA GAIN = 30dB 0.05
08180-052
0 0
0.2
0.4
0.6
0.8 GAIN+ (V)
1.0
1.2
1.4
1.6
Gain Control
The gain control interface, GAIN, is a differential input. VGAIN varies the gain of all VGAs through the interpolator by selecting the appropriate input stages connected to the input attenuator. For GAIN- at 0.8 V, the nominal GAIN+ range for 28.5 dB/V is 0 V to 1.6 V, with the best gain linearity from about 0.16 V to 1.44 V, where the error is typically less than 0.5 dB. For GAIN+ voltages greater than 1.44 V and less than 0.16 V, the error increases. The value of GAIN+ can exceed the supply voltage by 1 V without gain foldover. Gain control response time is less than 750 ns to settle within 10% of the final value for a change from minimum to maximum gain. The GAIN+ and GAIN- pins can be interfaced in one of two ways. Using a single-ended method, a Kelvin type of connection to ground can be used, as shown in Figure 60. For driving multiple devices, it is preferable to use a differential method, as shown in Figure 61. In either method, the GAIN+ and GAIN- pins should be dc-coupled and driven to accommodate a 1.6 V full-scale input.
08180-053
Figure 58. LNA with 21.3 dB Gain Setting/VGA Full-Scale Limitations
Variable Gain Amplifier (VGA)
The differential X-AMP VGA provides precise input attenuation and interpolation. It has a low input-referred noise of 3.8 nV/Hz and excellent gain linearity. A simplified block diagram is shown in Figure 59.
GAIN
GAIN INTERPOLATOR + gm POSTAMP
VIP
3.5dB
VIN
- POSTAMP
GAIN+
100 0.01F 50
0V TO 1.6V DC
0.01F
KELVIN CONNECTION
Figure 60. Single-Ended GAIN+, GAIN- Pin Configuration
Rev. 0 | Page 31 of 48
08180-054
Figure 59. Simplified VGA Schematic
GAIN-
AD9276
AVDD2 499 GAIN+ 100 0.01F GAIN- 100 0.01F 0.4V DC AT 0.8V CM 499 0.8V CM 523 10k
08180-055
31.3k 0.8V DC 50
AD8138
0.4V DC AT 0.8V CM 499
The antialiasing filter is a combination of a single-pole highpass filter and a second-order low-pass filter. The high-pass filter can be configured at a ratio of the low-pass filter cutoff. This is selectable through the SPI. The filter uses on-chip tuning to trim the capacitors and, in turn, to set the desired cutoff frequency and reduce variations. The default -3 dB low-pass filter cutoff is 1/3 or 1/4.5 the ADC sample clock rate. The cutoff can be scaled to 0.7, 0.8, 0.9, 1, 1.1, 1.2, or 1.3 times this frequency through the SPI. The cutoff tolerance is maintained from 8 MHz to 18 MHz.
4k C 30C
Figure 61. Differential GAIN+, GAIN- Pin Configuration
VGA Noise
In a typical application, a VGA compresses a wide dynamic range input signal to within the input span of an ADC. The input-referred noise of the LNA limits the minimum resolvable input signal, whereas the output-referred noise, which depends primarily on the VGA, limits the maximum instantaneous dynamic range that can be processed at any one particular gain control voltage. This latter limit is set in accordance with the total noise floor of the ADC. Output-referred noise as a function of GAIN+ is shown in Figure 11, Figure 12, and Figure 14 for the short-circuit input conditions. The input noise voltage is simply equal to the output noise divided by the measured gain at each point in the control range. The output-referred noise is a flat 60 nV/Hz (postamp gain = 24 dB) over most of the gain range because it is dominated by the fixed output-referred noise of the VGA. At the high end of the gain control range, the noise of the LNA and of the source prevails. The input-referred noise reaches its minimum value near the maximum gain control voltage, where the inputreferred contribution of the VGA is miniscule. At lower gains, the input-referred noise and, therefore, the noise figure, increase as the gain decreases. The instantaneous dynamic range of the system is not lost, however, because the input capacity increases as the input-referred noise increases. The contribution of the ADC noise floor has the same dependence. The important relationship is the magnitude of the VGA output noise floor relative to that of the ADC. Gain control noise is a concern in very low noise applications. Thermal noise in the gain control interface can modulate the channel gain. The resultant noise is proportional to the output signal level and is usually evident only when a large signal is present. The gain interface includes an on-chip noise filter, which significantly reduces this effect at frequencies above 5 MHz. Care should be taken to minimize noise impinging at the GAIN inputs. An external RC filter can be used to remove VGAIN source noise. The filter bandwidth should be sufficient to accommodate the desired control bandwidth.
4k 10k/n 4k
2k 4C 2k C
08180-056
30C
C = 0.8pF TO 5.1pF n = 0 TO 7
4k
Figure 62. Simplified Antialiasing Filter Schematic
Tuning is normally off to avoid changing the capacitor settings during critical times. The tuning circuit is enabled and disabled through the SPI. Initializing the tuning of the filter must be performed after initial power-up and after reprogramming the filter cutoff scaling or ADC sample rate. Occasional retuning during an idle time is recommended to compensate for temperature drift. A total of eight SPI-programmable settings allows the user to vary the high-pass filter cutoff frequency as a function of the low-pass cutoff frequency. Two examples are shown in Table 11: one is for an 8 MHz low-pass cutoff frequency, and the other is for an 18 MHz low-pass cutoff frequency. In both cases, as the ratio decreases, the amount of rejection on the low-end frequencies increases. Therefore, making the entire AAF frequency pass band narrow can reduce low frequency noise or maximize dynamic range for harmonic processing. Table 11. SPI-Selectable High-Pass Filter Cutoff Options
High-Pass Cutoff Frequency Low-Pass Cutoff Low-Pass Cutoff = 8 MHz = 18 MHz 387 kHz 872 kHz 698 kHz 1.571 MHz 1.010 MHz 2.273 MHz 1.323 MHz 2.978 MHz 1.638 MHz 3.685 MHz 1.953 MHz 4.394 MHz 2.270 MHz 5.107 MHz 2.587 MHz 5.822 MHz
Antialiasing Filter (AAF)
The filter that the signal reaches prior to the ADC is used to reject dc signals and to band limit the signal for antialiasing. Figure 62 shows the architecture of the filter.
SPI Setting 0 1 2 3 4 5 6 7
1
Ratio1 20.65 11.45 7.92 6.04 4.88 4.10 3.52 3.09
Ratio = low-pass filter cutoff frequency/high-pass filter cutoff frequency.
Rev. 0 | Page 32 of 48
AD9276
ADC
The AD9276 uses a pipelined ADC architecture. The quantized output from each stage is combined into a 12-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on preceding samples. Sampling occurs on the rising edge of the clock. The output staging block aligns the data, corrects errors, and passes the data to the output buffers. The data is then serialized and aligned to the frame and output clocks.
3.3V 50 * VFAC3 OUT
AD951x FAMILY
0.1F CLK LVDS DRIVER CLK 100 0.1F CLK-
08180-059
0.1F CLK+
ADC
0.1F
*50 RESISTOR IS OPTIONAL.
Figure 65. Differential LVDS Sample Clock
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9276 sample clock inputs (CLK+ and CLK-) should be clocked with a differential signal. This signal is typically ac-coupled into the CLK+ and CLK- pins via a transformer or capacitors. These pins are biased internally and require no additional bias. Figure 63 shows the preferred method for clocking the AD9276. A low jitter clock source, such as the Valpey Fisher oscillator VFAC3-BHL-50 MHz, is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the secondary transformer limit clock excursions into the AD9276 to approximately 0.8 V p-p differential. This helps to prevent the large voltage swings of the clock from feeding through to other portions of the AD9276, and it preserves the fast rise and fall times of the signal, which are critical to low jitter performance.
3.3V MINI-CIRCUITS ADT1-1WT, 1:1Z 0.1F XFMR 0.1F 0.1F SCHOTTKY DIODES: HSM2812
In some applications, it is acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, CLK+ should be driven directly from a CMOS gate, and the CLK- pin should be bypassed to ground with a 0.1 F capacitor in parallel with a 39 k resistor (see Figure 66). Although the CLK+ input circuit supply is AVDD1 (1.8 V), this input is designed to withstand input voltages of up to 3.3 V, making the selection of the drive logic voltage very flexible.
3.3V VFAC3 OUT
0.1F
CLK
AD951x FAMILY
OPTIONAL 0.1F 100
50 *
CMOS DRIVER
CLK
CLK+
ADC
CLK-
08180-060
0.1F
0.1F
*50 RESISTOR IS OPTIONAL.
39k
Figure 66. Single-Ended 1.8 V CMOS Sample Clock
3.3V VFAC3 OUT
0.1F
CLK
AD951x FAMILY
OPTIONAL 0.1F 100
0.1F OUT VFAC3
CLK+
50 100
50 *
ADC
CLK-
08180-057
CMOS DRIVER
CLK
CLK+
ADC
0.1F CLK-
08180-061
0.1F
Figure 63. Transformer-Coupled Differential Clock
If a low jitter clock is available, another option is to ac-couple a differential PECL signal to the sample clock input pins, as shown in Figure 64. The AD951x family of clock drivers offers excellent jitter performance.
3.3V 50* VFAC3 OUT
*50 RESISTOR IS OPTIONAL.
Figure 67. Single-Ended 3.3 V CMOS Sample Clock
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to the clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9276 contains a duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9276. When the DCS is on, noise and distortion performance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, keep in mind that the dynamic range performance can be affected when operated in this mode. See Table 18 for more details on using this feature.
AD951x FAMILY
0.1F CLK PECL DRIVER CLK 240 240
08180-058
0.1F CLK+ 100 0.1F CLK-
ADC
0.1F
*50 RESISTOR IS OPTIONAL.
Figure 64. Differential PECL Sample Clock
Rev. 0 | Page 33 of 48
AD9276
The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately eight clock cycles to allow the DLL to acquire and lock to the new rate.
CURRENT (mA)
400 350 300 250 IAVDD1 , 65MSPS SPEED GRADE 200 150 100 50 0 IDRVDD IAVDD1 , 40MSPS SPEED GRADE IAVDD1 , 80MSPS SPEED GRADE
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated as follows: SNR Degradation = 20 x log10(1/2 x x fA x tJ) In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter. IF undersampling applications are particularly sensitive to jitter (see Figure 68). The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9276. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources, such as the Valpey Fisher VFAC3 series. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock during the last step. Refer to the AN-501 Application Note and the AN-756 Application Note for more in-depth information about how jitter performance relates to ADCs (visit www.analog.com).
130 120 110 100 16 BITS 14 BITS 12 BITS 10 BITS 8 BITS 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps 10 100 ANALOG INPUT FREQUENCY (MHz) 1000
08180-062
0
10
20
30
40
50
60
70
80
SAMPLING FREQUENCY (MSPS)
Figure 69. Supply Current vs. fSAMPLE for fIN = 5 MHz
220 215 210 80MSPS SPEED GRADE
POWER/CHANNEL (mW)
205 200 195 190 185 180 175 0 10 20 30 40 50 60 70 80
08180-064
65MSPS SPEED GRADE
40MSPS SPEED GRADE
170
RMS CLOCK JITTER REQUIREMENT
SAMPLING FREQUENCY (MSPS)
Figure 70. Power per Channel vs. fSAMPLE for fIN = 5 MHz
SNR (dB)
90 80 70 60 50 40 30 1
The AD9276 features scalable LNA bias currents (see Table 18, Register 0x12). The default LNA bias current settings are high. Figure 71 shows the typical reduction of AVDD2 current with each bias setting. It is also recommended that the LNA offset be adjusted using Register 0x10 (see Table 18) when the LNA bias setting is low.
HIGH
LNA BIAS SETTING
Figure 68. Ideal SNR vs. Input Frequency and Jitter
MID-HIGH
Power Dissipation and Power-Down Mode
As shown in Figure 69 and Figure 70, the power dissipated by the AD9276 is proportional to its sample rate. The digital power dissipation does not vary significantly because it is determined primarily by the DRVDD supply and the bias current of the LVDS output drivers.
MID-LOW
LOW
08180-065
0
50
100 150 200 250 300 TOTAL AVDD2 CURRENT (mA)
350
400
Figure 71. AVDD2 Current at Different LNA Bias Settings, fSAMPLE = 40 MSPS
Rev. 0 | Page 34 of 48
08180-063
AD9276
By asserting the PDWN pin high, the AD9276 is placed into power-down mode. In this state, the device typically dissipates 5 mW. During power-down, the LVDS output drivers are placed into a high impedance state. The AD9276 returns to normal operating mode when the PDWN pin is pulled low. This pin is both 1.8 V and 3.3 V tolerant. By asserting the STBY pin high, the AD9276 is placed into a standby mode. In this state, the device typically dissipates 175 mW. During standby, the entire part is powered down except for the internal references. The LVDS output drivers are placed into a high impedance state. This mode is well suited for applications that require power savings because it allows the device to be powered down when not in use and then quickly powered up. The time to power the device back up is also greatly reduced. The AD9276 returns to normal operating mode when the STBY pin is pulled low. This pin is both 1.8 V and 3.3 V tolerant. In power-down mode, low power dissipation is achieved by shutting down the reference, reference buffer, PLL, and biasing networks. The decoupling capacitors on VREF are discharged when entering power-down mode and must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in the power-down mode: shorter cycles result in proportionally shorter wake-up times. To restore the device to full operation, approximately 0.5 ms is required when using the recommended 1 F and 0.1 F decoupling capacitors on the VREF pin and the 0.01 F decoupling capacitors on the GAIN pins. Most of this time is dependent on the gain decoupling: higher value decoupling capacitors on the GAIN pins result in longer wake-up times. A number of other power-down options are available when using the SPI port interface. The user can individually power down each channel or put the entire device into standby mode. This allows the user to keep the internal PLL powered up when fast wake-up times are required. The wake-up time is slightly dependent on gain. To achieve a 1 s wake-up time when the device is in standby mode, 0.8 V must be applied to the GAIN pins. See Table 18 for more details on using these features. The AD9276 LVDS outputs facilitate interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments. Single point-to-point network topologies are recommended with a 100 termination resistor placed as close to the receiver as possible. No far-end receiver termination and poor differential trace routing may result in timing errors. It is recommended that the trace length be no longer than 24 inches and that the differential output traces be kept close together and at equal lengths. An example of the FCO, DCO, and data stream with proper trace length and position is shown in Figure 72.
CH1 500mV/DIV = DCO CH2 500mV/DIV = DATA CH3 500mV/DIV = FCO
5.0ns/DIV
Figure 72. LVDS Output Timing Example in ANSI-644 Mode (Default)
An example of the LVDS output using the ANSI-644 standard (default) data eye and a time interval error (TIE) jitter histogram with trace lengths less than 24 inches on regular FR-4 material is shown in Figure 73. Figure 74 shows an example of the trace lengths exceeding 24 inches on regular FR-4 material. Notice that the TIE jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position; therefore, the user must determine whether the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches. Additional SPI options allow the user to further increase the internal termination (and therefore increase the current) of all eight outputs in order to drive longer trace lengths (see Figure 75). Even though this produces sharper rise and fall times on the data edges, is less prone to bit errors, and improves frequency distribution (see Figure 75), the power dissipation of the DRVDD supply increases when this option is used. In cases that require increased driver strength to the DCO and FCO outputs because of load mismatch, the user can double the drive strength by setting Bit 0 in Register 0x15. Note that this feature cannot be used with Bits[5:4] in Register 0x15 because these bits take precedence over this feature. See Table 18 for more details.
DIGITAL OUTPUTS AND TIMING
The AD9276 differential outputs conform to the ANSI-644 LVDS standard on default power-up. This can be changed to a low power, reduced signal option similar to the IEEE 1596.3 standard via the SPI, using Register 0x14, Bit 6. This LVDS standard can further reduce the overall power dissipation of the device by approximately 36 mW. The LVDS driver current is derived on chip and sets the output current at each output equal to a nominal 3.5 mA. A 100 differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver.
Rev. 0 | Page 35 of 48
08180-066
AD9276
600 400 EYE: ALL BITS ULS: 2398/2398
EYE DIAGRAM VOLTAGE (V)
400 300 200 100 0 -100 -200 -300 -400 EYE: ALL BITS ULS: 2399/2399
EYE DIAGRAM VOLTAGE (V)
200 100 0 -100 -200 -400 -600
-1.5ns
-1.0ns
-0.5ns
0ns
0.5ns
1.0ns
1.5ns
-1.5ns
-1.0ns
-0.5ns
0ns
0.5ns
1.0ns
1.5ns
25
25
TIE JITTER HISTOGRAM (Hits)
15
TIE JITTER HISTOGRAM (Hits)
20
20
15
10
10
5
5
08180-067
0 -200ps
-100ps
0ps
100ps
200ps
0 -200ps
-100ps
0ps
100ps
200ps
Figure 73. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths of Less Than 24 Inches on Standard FR-4
Figure 74. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths of Greater Than 24 Inches on Standard FR-4
Rev. 0 | Page 36 of 48
08180-068
AD9276
600 EYE: ALL BITS 400
EYE DIAGRAM VOLTAGE (V)
ULS: 2396/2396
200
0
-200
Two output clocks are provided to assist in capturing data from the AD9276. DCO is used to clock the output data and is equal to six times the sampling clock rate. Data is clocked out of the AD9276 and must be captured on the rising and falling edges of DCO, which supports double data rate (DDR) capturing. The frame clock output (FCO) is used to signal the start of a new output byte and is equal to the sampling clock rate. See the timing diagram shown in Figure 2 for more information. When using the serial port interface (SPI), the DCO phase can be adjusted in 60 increments relative to the data edge. This enables the user to refine system timing margins if required. The default DCO timing, as shown in Figure 2, is 180 relative to the output data edge. An 8-, 10-, or 14-bit serial stream can also be initiated from the SPI. This allows the user to implement different serial streams and to test the device's compatibility with lower and higher resolution systems. When changing the resolution to an 8- or 10-bit serial stream, the data stream is shortened. When using the 14-bit option, the data stream stuffs two 0s at the end of the normal 12-bit serial data. When using the SPI, all of the data outputs can also be inverted from their nominal state by setting Bit 2 in the output mode register (Address 0x14). This is not to be confused with inverting the serial stream to an LSB first mode. In default mode, as shown in Figure 2, the MSB is represented first in the data output serial stream. However, this order can be inverted so that the LSB is represented first in the data output serial stream (see Figure 3). There are 12 digital output test pattern options available that can be initiated through the SPI. This feature is useful when validating receiver capture and timing. Refer to Table 13 for the output bit sequencing options available. Some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. Note that some patterns may not adhere to the data format select option. In addition, custom user-defined test patterns can be assigned in the user pattern registers (Address 0x19 through Address 0x1C). All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths in order to verify data capture to the receiver. The PN sequence short pattern produces a pseudorandom bit sequence that repeats itself every 29 - 1 bits, or 511 bits. A description of the PN sequence short and how it is generated can be found in Section 5.1 of the ITU-T O.150 (05/96) standard. The only difference is that the starting value is a specific value instead of all 1s (see Table 14 for the initial values).
-400
-600
-1.5ns
-1.0ns
-0.5ns
0ns
0.5ns
1.0ns
1.5ns
25
TIE JITTER HISTOGRAM (Hits)
20
15
10
5
0 -200ps
-100ps
0ps
100ps
200ps
Figure 75. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Termination On and Trace Lengths of Greater Than 24 Inches on Standard FR-4
The format of the output data is offset binary by default. Table 12 provides an example of the output coding format. To change the output data format to twos complement, see the Memory Map section. Table 12. Digital Output Coding
Code 4095 2048 2047 0 (VIN+) - (VIN-), Input Span = 2 V p-p (V) +1.00 0.00 -0.000488 -1.00 Digital Output Offset Binary (D11 to D0) 1111 1111 1111 1000 0000 0000 0111 1111 1111 0000 0000 0000
Data from each ADC is serialized and provided on a separate channel. The data rate for each serial stream is equal to 12 bits times the sample clock rate, with a maximum of 960 Mbps (12 bits x 80 MSPS = 960 Mbps). The lowest typical conversion rate is 10 MSPS, but the PLL can be set up for encode rates as low as 5 MSPS via the SPI if lower sample rates are required for a specific application. See Table 18 for details on enabling this feature.
Rev. 0 | Page 37 of 48
08180-069
AD9276
Table 13. Flexible Output Test Modes
Output Test Mode Bit Sequence 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Pattern Name Off (default) Midscale short +Full-scale short -Full-scale short Checkerboard PN sequence long PN sequence short One-/zero-word toggle User input 1-/0-bit toggle 1x sync One bit high Mixed bit frequency Digital Output Word 1 N/A 1000 0000 0000 1111 1111 1111 0000 0000 0000 1010 1010 1010 N/A N/A 1111 1111 1111 Register 0x19 and Register 0x1A 1010 1010 1010 0000 0011 1111 1000 0000 0000 1010 0011 0011 Digital Output Word 2 N/A Same Same Same 0101 0101 0101 N/A N/A 0000 0000 0000 Register 0x1B and Register 0x1C N/A N/A N/A N/A Subject to Data Format Select N/A Yes Yes Yes No Yes Yes No No No No No No
The PN sequence long pattern produces a pseudorandom bit sequence that repeats itself every 223 - 1 bits, or 8,388,607 bits. A description of the PN sequence long and how it is generated can be found in Section 5.6 of the ITU-T O.150 (05/96) standard. The only differences are that the starting value is a specific value instead of all 1s and that the AD9276 inverts the bit stream with relation to the ITU-T standard (see Table 14 for the initial values). Table 14. PN Sequence
Sequence PN Sequence Short PN Sequence Long Initial Value 0x0DF 0x29B80A First Three Output Samples (MSB First) 0xDF9, 0x353, 0x301 0x591, 0xFD7, 0x0A3
RBIAS Pin
To set the internal core bias current of the ADC, place a resistor nominally equal to 10.0 k to ground at the RBIAS pin. Using a resistor other than the recommended 10.0 k resistor for RBIAS degrades the performance of the device. Therefore, it is imperative that at least a 1% tolerance on this resistor be used to achieve consistent performance.
Voltage Reference
A stable and accurate 0.5 V voltage reference is built into the AD9276. This is gained up internally by a factor of 2, setting VREF to 1.0 V, which results in a full-scale differential input span of 2.0 V p-p for the ADC. VREF is set internally by default, but the VREF pin can be driven externally with a 1.0 V reference to achieve more accuracy. However, the AD9276 does not support ADC full-scale ranges below 2.0 V p-p. When applying the decoupling capacitors to the VREF pin, use ceramic, low ESR capacitors. These capacitors should be close to the reference pin and on the same layer of the PCB as the AD9276. The VREF pin should have both a 0.1 F capacitor and a 1 F capacitor connected in parallel to the analog ground. These capacitor values are recommended for the ADC to properly settle and acquire the next valid sample. The reference settings can be selected using the SPI. The settings allow two options: using the internal reference or using an external reference. The internal reference option is the default setting and has a resulting differential span of 2 V p-p. Table 15. SPI-Selectable Reference Settings
SPI-Selected Mode External Reference Internal Reference (Default) Resulting VREF (V) N/A 1.0 Resulting Differential Span (V p-p) 2 x external reference 2.0
See the Memory Map section for information on how to change these additional digital output timing features through the SPI.
SDIO Pin
This pin is required to operate the SPI. It has an internal 30 k pull-down resistor that pulls this pin low and is only 1.8 V tolerant. If applications require that this pin be driven from a 3.3 V logic level, insert a 1 k resistor in series with this pin to limit the current.
SCLK Pin
This pin is required to operate the SPI port interface. It has an internal 30 k pull-down resistor that pulls this pin low and is both 1.8 V and 3.3 V tolerant.
CSB Pin
This pin is required to operate the SPI port interface. It has an internal 70 k pull-up resistor that pulls this pin high and is both 1.8 V and 3.3 V tolerant.
Rev. 0 | Page 38 of 48
AD9276 SERIAL PORT INTERFACE (SPI)
The AD9276 serial port interface allows the user to configure the signal chain for specific functions or operations through a structured register space provided inside the chip. The SPI offers the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields, as documented in the Memory Map section. Detailed operational information can be found in the Analog Devices, Inc., AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Three pins define the serial port interface, or SPI: SCLK, SDIO, and CSB (see Table 16). The SCLK (serial clock) pin is used to synchronize the read and write data presented to the device. The SDIO (serial data input/output) pin is a dual-purpose pin that allows data to be sent to and read from the internal memory map registers of the device. The CSB (chip select bar) pin is an active low control that enables or disables the read and write cycles. Table 16. Serial Port Pins
Pin SCLK SDIO Function Serial clock. Serial shift clock input. SCLK is used to synchronize serial interface reads and writes. Serial data input/output. Dual-purpose pin that typically serves as an input or an output, depending on the instruction sent and the relative position in the timing frame. Chip select bar (active low). This control gates the read and write cycles.
CSB
The falling edge of CSB in conjunction with the rising edge of SCLK determines the start of the framing sequence. During an instruction phase, a 16-bit instruction is transmitted, followed by one or more data bytes, which is determined by Bit Field W0 and Bit Field W1. An example of the serial timing and its definitions can be found in Figure 76 and Table 17.
tDS tS
CSB
tHIGH tDH tLOW
tCLK
tH
SCLK
DON'T CARE
DON'T CARE
SDIO
DON'T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
DON'T CARE
Figure 76. Serial Timing Details
Table 17. Serial Timing Definitions
Parameter tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO tDIS_SDIO Timing (ns min) 5 2 40 5 2 16 16 10 10 Description Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the clock Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 76) Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 76)
Rev. 0 | Page 39 of 48
08180-072
AD9276
During normal operation, CSB is used to signal to the device that SPI commands are to be received and processed. When CSB is brought low, the device processes SCLK and SDIO to execute instructions. Normally, CSB remains low until the communication cycle is complete. However, if connected to a slow device, CSB can be brought high between bytes, allowing older microcontrollers enough time to transfer data into shift registers. CSB can be stalled when transferring one, two, or three bytes of data. When W0 and W1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until CSB is taken high to end the communication cycle. This allows complete memory transfers without the need for additional instructions. Regardless of the mode, if CSB is taken high in the middle of a byte transfer, the SPI state machine is reset and the device waits for a new instruction. In addition to the operation modes, the SPI port can be configured to operate in different manners. For applications that do not require a control port, the CSB line can be tied and held high. This places the remainder of the SPI pins in their secondary mode (see the AN-877 Application Note). CSB can also be tied low to enable 2-wire mode. When CSB is tied low, SCLK and SDIO are the only pins required for communication. Although the device is synchronized during power-up, caution must be exercised when using 2-wire mode to ensure that the serial port remains synchronized with the CSB line. When operating in 2-wire mode, it is recommended that a 1-, 2-, or 3-byte transfer be used exclusively. Without an active CSB line, streaming mode can be entered but not exited. In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used to both program the chip and to read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the serial data input/output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. Data can be sent in MSB first mode or LSB first mode. MSB first mode is the default at power-up and can be changed by adjusting the configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
HARDWARE INTERFACE
The pins described in Table 16 constitute the physical interface between the user's programming device and the serial port of the AD9276. The SCLK and CSB pins function as inputs when using the SPI. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. If multiple SDIO pins share a common connection, ensure that proper VOH levels are met. Figure 77 shows the number of SDIO pins that can be connected together and the resulting VOH level, assuming the same load for each AD9276.
1.800 1.795 1.790 1.785 1.780 1.775 1.770 1.765 1.760 1.755 1.750 1.745 1.740 1.735 1.730 1.725 1.720 1.715
VOH (V)
0
10
20
30
40
50
60
70
80
90
100
NUMBER OF SDIO PINS CONNECTED TOGETHER
Figure 77. SDIO Pin Loading
This interface is flexible enough to be controlled by either serial PROMs or PIC microcontrollers, providing the user with an alternative method, other than a full SPI controller, for programming the device (see the AN-812 Application Note).
Rev. 0 | Page 40 of 48
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AD9276 MEMORY MAP
READING THE MEMORY MAP TABLE
Each row in the memory map register table has eight bit locations. The memory map is roughly divided into three sections: the chip configuration register map (Address 0x00 to Address 0x02), the device index and transfer register map (Address 0x04 to Address 0xFF), and the program register map (Address 0x08 to Address 0x2D). The leftmost column of the memory map indicates the register address, and the default value is shown in the second rightmost column. The Bit 7 (MSB) column is the start of the default hexadecimal value given. For example, Address 0x09, the clock register, has a default value of 0x01, meaning that Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. This setting is the default for the duty cycle stabilizer in the on condition. By writing a 0 to Bit 0 of this address, followed by 0x01 in Register 0xFF (the transfer bit), the duty cycle stabilizer is turned off. It is important to follow each writing sequence with a transfer bit to update the SPI registers. All registers except Register 0x00, Register 0x02, Register 0x04, Register 0x05, and Register 0xFF are buffered with a master slave latch and require writing to the transfer bit. For more information on this and other functions, consult the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
RESERVED LOCATIONS
Undefined memory locations should not be written to except when writing the default values suggested in this data sheet. Addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up.
DEFAULT VALUES
After a reset, critical registers are automatically loaded with default values. These values are indicated in Table 18, where an X refers to an undefined feature.
LOGIC LEVELS
An explanation of various registers follows: "bit is set" is synonymous with "bit is set to Logic 1" or "writing Logic 1 for the bit." Similarly, "bit is cleared" is synonymous with "bit is set to Logic 0" or "writing Logic 0 for the bit."
Rev. 0 | Page 41 of 48
AD9276
Table 18. AD9276 Memory Map Registers
Addr. Bit 7 (Hex) Register Name (MSB) Chip Configuration Registers 0x00 chip_port_config 0 Bit 6 LSB first 1 = on 0 = off (default) Bit 5 Soft reset 1 = on 0 = off (default) Bit 4 1 Bit 3 1 Bit 2 Soft reset 1 = on 0 = off (default) Bit 1 LSB first 1 = on 0 = off (default) Bit 0 (LSB) 0 Default Value 0x18 Comments Nibbles should be mirrored so that LSB or MSB first mode is set correctly regardless of shift mode. Default is unique chip ID, different for each device. Read-only register. Child ID used to differentiate ADC speed power modes.
0x01
chip_id
Chip ID Bits[7:0] (AD9276 = 0x72, default)
0x02
chip_grade
X
X
Child ID[5:4] (identify device variants of chip ID) 00: Mode I (40 MSPS) (default) 01: Mode II (65 MSPS) 10: Mode III (80 MSPS) X X
X
X
X
X
0x00
Device Index and Transfer Registers 0x04 device_index_2 X
X
0x05
device_index_1
X
X
0xFF
device_update
X
X
Clock Channel DCO 1 = on 0 = off (default) X
Clock Channel FCO 1 = on 0 = off (default) X
Data Channel H 1 = on (default) 0 = off Data Channel D 1 = on (default) 0 = off X
Data Channel G 1 = on (default) 0 = off Data Channel C 1 = on (default) 0 = off X
Data Channel F 1 = on (default) 0 = off Data Channel B 1 = on (default) 0 = off X
Data Channel E 1 = on (default) 0 = off Data Channel A 1 = on (default) 0 = off SW transfer 1 = on 0 = off (default)
0x0F
Bits are set to determine which on-chip device receives the next write command. Bits are set to determine which on-chip device receives the next write command. Synchronously transfers data from the master shift register to the slave. Determines generic modes of chip operation (global).
0x0F
0x00
Program Function Registers 0x08 modes X
X
X
0x09
clock
X
X
X
LNA input impedance 1 = 5 k 0 = 15 k (default) X
0
Internal power-down mode 000 = chip run (default) 001 = full power-down 010 = standby 011 = reset 100 = CW mode (TGC PDWN) X X DCS 1 = on (default) 0 = off
0x00
X
0x01
0x0D
test_io
User test mode 00 = off (default) 01 = on, single alternate 10 = on, single once 11 = on, alternate once
Reset PN long gen 1 = on 0 = off (default)
Reset PN short gen 1 = on 0 = off (default)
0x0E
GPO outputs
X
X
X
X
Output test mode--see Table 13 0000 = off (default) 0001 = midscale short 0010 = +FS short 0011 = -FS short 0100 = checkerboard output 0101 = PN sequence long 0110 = PN sequence short 0111 = one-/zero-word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1x sync 1011 = one bit high 1100 = mixed bit frequency (format determined by output_mode) General-purpose digital outputs
0x00
Turns the internal duty cycle stabilizer (DCS) on and off (global). When this register is set, the test data is placed on the output pins in place of normal data. (Local, except for PN sequence.)
0x00
Values placed on GPO[0:3] pins (global).
Rev. 0 | Page 42 of 48
AD9276
Addr. (Hex) 0x0F Register Name flex_channel_input Bit 7 Bit 0 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) X X X X Filter cutoff frequency control 0000 = 1.3 x 1/3 x fSAMPLE 0001 = 1.2 x 1/3 x fSAMPLE 0010 = 1.1 x 1/3 x fSAMPLE 0011 = 1.0 x 1/3 x fSAMPLE (default) 0100 = 0.9 x 1/3 x fSAMPLE 0101 = 0.8 x 1/3 x fSAMPLE 0110 = 0.7 x 1/3 x fSAMPLE 1000 = 1.3 x 1/4.5 x fSAMPLE 1001 = 1.2 x 1/4.5 x fSAMPLE 1010 = 1.1 x 1/4.5 x fSAMPLE 1011 = 1.0 x 1/4.5 x fSAMPLE 1100 = 0.9 x 1/4.5 x fSAMPLE 1101 = 0.8 x 1/4.5 x fSAMPLE 1110 = 0.7 x 1/4.5 x fSAMPLE X X 6-bit LNA offset adjustment 10 0000 for LNA bias high, mid-high, mid-low (default) 10 0001 for LNA bias low LNA gain X X X X PGA gain 00 = 15.6 dB 00 = 21 dB 01 = 17.9 dB 01 = 24 dB (default) 10 = 21.3 dB 10 = 27 dB (default) 11 = 30 dB X X X X 1 X LNA bias 00 = high (default) 01 = mid-high 10 = mid-low 11 = low Data format select X X X Output X 0 = LVDS 00 = offset binary invert ANSI-644 (default) enable (default) 01 = twos 1 = on 1 = LVDS complement 0 = off low power, (default) (IEEE 1596.3 similar) X X X DCO X X Output driver and termination FCO 00 = none (default) 2x drive 01 = 200 strength 10 = 100 1 = on 11 = 100 0 = off (default) Default Value 0x30 Comments Antialiasing filter cutoff (global).
0x10
flex_offset
0x20
0x11
flex_gain
0x06
LNA force offset correction (local). LNA and PGA gain adjustment (global).
0x12
bias_current
0x08
LNA bias current adjustment (global).
0x14
output_mode
0x00
Configures the outputs and the format of the data (Bits[7:3] and Bits[1:0] are global; Bit 2 is local).
0x15
output_adjust
0x00
0x16
output_phase
X
X
X
X
0x18
flex_vref
X
0= internal reference 1= external reference
X
X
0011 = output clock phase adjust (0000 through 1010) (Default: 180 relative to data edge) 0000 = 0 relative to data edge 0001 = 60 relative to data edge 0010 = 120 relative to data edge 0011 = 180 relative to data edge 0100 = 240 relative to data edge 0101 = 300 relative to data edge 0110 = 360 relative to data edge 0111 = 420 relative to data edge 1000 = 480 relative to data edge 1001 = 540 relative to data edge 1010 = 600 relative to data edge 1011 to 1111 = 660 relative to data edge X X X X
0x03
Determines LVDS or other output properties. Primarily functions to set the LVDS span and common-mode levels in place of an external resistor (Bits[7:1] are global; Bit 0 is local). On devices that utilize global clock divide, determines which phase of the divider output is used to supply the output clock. Internal latching is unaffected.
0x00
Select internal reference (recommended default) or external reference (global).
Rev. 0 | Page 43 of 48
AD9276
Addr. (Hex) 0x19 Register Name user_patt1_lsb Bit 7 (MSB) B7 Bit 6 B6 Bit 5 B5 Bit 4 B4 Bit 3 B3 Bit 2 B2 Bit 1 B1 Bit 0 (LSB) B0 Default Value 0x00 Comments User-Defined Pattern 1, LSB (global). User-Defined Pattern 1, MSB (global). User-Defined Pattern 2, LSB (global). User-Defined Pattern 2, MSB (global). Serial stream control (global).
0x1A
user_patt1_msb
B15
B14
B13
B12
B11
B10
B9
B8
0x00
0x1B
user_patt2_lsb
B7
B6
B5
B4
B3
B2
B1
B0
0x00
0x1C
user_patt2_msb
B15
B14
B13
B12
B11
B10
B9
B8
0x00
0x21
serial_control
LSB first 1 = on 0 = off (default)
X
X
X
0x22
serial_ch_stat
X
X
X
X
<10 MSPS, low encode rate mode 1 = on 0 = off (default) X
Serial bit stream length 000 = 12 bits (default, normal bit stream) 001 = 8 bits 010 = 10 bits 011 = 12 bits 100 = 14 bits
0x00
X
Channel output reset 1 = on 0 = off (default)
Channel powerdown 1 = on 0 = off (default)
0x00
Used to power down individual sections of a converter (local).
0x2B
flex_filter
X
Enable automatic low-pass tuning 1 = on (selfclearing)
X
X
0x2C
analog_input
X
X
X
X
0x2D
CW Doppler I/Q demodulator phase
X
X
X
CW Doppler channel enable 1 = on 0 = off
High-pass filter cutoff 0000 = fLP/20.7 0001 = fLP/11.5 0010 = fLP/7.9 0011 = fLP/6.0 0100 = fLP/4.9 0101 = fLP/4.1 0110 = fLP/3.5 0111 = fLP/3.1 X X LO-x, LOSW-x connection 00 = (-)LNA output, high-Z 01 = (-)LNA output, (-)LNA output 10 = (-)LNA output, (+)LNA output 11 = high-Z, high-Z I/Q demodulator phase 0000 = 0 0001 = 22.5 0010 = 45 0011 = 67.5 0100 = 90 0101 = 112.5 0110 = 135 0111 = 157.5 1000 = 180 1001 = 202.5 1010 = 225 1011 = 247.5 1100 = 270 1101 = 292.5 1110 = 315 1111 = 337.5
0x00
Filter cutoff (global). (fLP = low-pass filter cutoff frequency.)
0x00
LNA active termination/input impedance (global).
Phase of demodulators (local).
Rev. 0 | Page 44 of 48
AD9276 APPLICATIONS INFORMATION
POWER AND GROUND RECOMMENDATIONS
When connecting power to the AD9276, it is recommended that two separate 1.8 V supplies be used: one for analog (AVDD) and one for digital (DRVDD). If only one 1.8 V supply is available, it should be routed to the AVDD1 pin first and then tapped off and isolated with a ferrite bead or a filter choke preceded by decoupling capacitors for the DRVDD pin. The user should employ several decoupling capacitors on all supplies to cover both high and low frequencies. Locate these capacitors close to the point of entry at the PCB level and close to the part, with minimal trace lengths. A single PCB ground plane should be sufficient when using the AD9276. With proper decoupling and smart partitioning of the analog, digital, and clock sections of the PCB, optimum performance can be easily achieved.
EXPOSED PADDLE THERMAL HEAT SLUG RECOMMENDATIONS
It is required that the exposed paddle on the underside of the device be connected to analog ground to achieve the best electrical and thermal performance of the AD9276. An exposed continuous copper plane on the PCB should mate to the AD9276 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be solder-filled or plugged with nonconductive epoxy. To maximize the coverage and adhesion between the device and the PCB, partition the continuous copper plane into several uniform sections by overlaying a silkscreen or solder mask on the PCB. This ensures several tie points between the AD9276 and the PCB during the reflow process, whereas using one continuous plane with no partitions guarantees only one tie point. See Figure 78 for a PCB layout example. For detailed information about packaging and for more PCB layout examples, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), at www.analog.com.
SILKSCREEN PARTITION PIN 1 INDICATOR
Figure 78. Typical PCB Layout
Rev. 0 | Page 45 of 48
08180-070
AD9276 OUTLINE DIMENSIONS
0.75 0.60 0.45 1.20 MAX
100 1 PIN 1
16.00 BSC SQ 14.00 BSC SQ
76 75 76 75 100 1
TOP VIEW
(PINS DOWN)
EXPOSED PAD
9.50 SQ
1.05 1.00 0.95
0 MIN
0.15 0.05
SEATING PLANE
0.20 0.09 7 3.5 0 0.08 MAX COPLANARITY
25 26
51 50
51 50
BOTTOM VIEW (PINS UP) 26
25
VIEW A
0.50 BSC LEAD PITCH
0.27 0.22 0.17
VIEW A
ROTATED 90 CCW
COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
100908-A
Figure 79. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-100-3) Dimensions shown in millimeters
ORDERING GUIDE
Model AD9276BSVZ 1 AD9276-65EBZ1 AD9276-80KITZ1
1
Temperature Range -40C to +85C
Package Description 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Evaluation Board Evaluation Board and High Speed FPGA-Based Data Capture Board
Package Option SV-100-3
Z = RoHS Compliant Part.
Rev. 0 | Page 46 of 48
AD9276 NOTES
Rev. 0 | Page 47 of 48
AD9276 NOTES
(c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08180-0-7/09(0)
Rev. 0 | Page 48 of 48

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